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| 型号： | LT1575CS8-3.3 |
| 厂商： | Linear Technology |
| 文件页数： | 12/20页 |
| 文件大小： | 312K |
| 描述： | IC REG CTRLR SGL 3.3V 8SOIC |
| 标准包装： | 100 |
| 类型： | 正，固定式 |
| 输出数： | 1 |
| 输出电压： | 3.3V |
| 电流 - 电源： | 12mA |
| 输入电压： | 10 V ~ 20 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 管件 |
12
LT1575/LT1577
APPLICATIONS INFORMATION
U
U
U
diagram and clamps the positive swing of the COMP node
in the main error amplifier to a voltage that provides an
output load current of 50mV/R
SENSE
. This action contin-
ues as long as the output current overload persists. The
second event is that a timer circuit activates at the SHDN
pin. This pin is normally held low by a 5礎 active pull-down
that limits to H 100mV above ground. When current limit
activates, the 5礎 pull-down turns off and a 15礎 pull-up
current source turns on. Placing a capacitor in series with
the SHDN pin to ground generates a programmable time
ramp voltage.
The SHDN pin is also the positive input of COMP1. The
negative input is tied to the internal 1.21V reference. When
the SHDN pin ramps above V
REF
, the comparator drives
Q4 and Q5. This action pulls the COMP and GATE pins low
and latches the external MOSFET drive off. This condition
reduces the MOSFET power dissipation to zero. The time
period until the latched-off condition occurs is typically
equal to C
SHUT
(1.11V)/15礎. For example, a 1礔 capacitor
on the SHDN pin yields a 74ms ramp time. In short, this
unique circuit block performs a current limit time-out
function that latches off the regulator drive after a pre-
defined time period. The time-out period selected is a
function of system requirements including start-up and
safe operating area. The SHDN pin is internally clamped to
typically 1.85V by Q6 and R2. The comparator tied to the
SHDN pin has 100mV of typical hysteresis to provide
noise immunity. The hysteresis is especially useful when
using the SHDN pin for thermal shutdown.
Restoring normal operation after the load current fault is
cleared is accomplished in two ways. One option is to
recycle the nominal 12V LT1575 supply voltage as long as
an external bleed path for the Shutdown pin capacitor is
provided. The second option is to provide an active reset
circuit that pulls the SHDN pin below V
REF
. Pulling the
SHDN pin below V
REF
turns off the 15礎 pull-up current
source and reactivates the 5礎 pull-down. If the SHDN pin
is held below V
REF
during a fault condition, the regulator
continues to operate in current limit into a short. This
action requires being able to sink 15礎 from the SHDN pin
at less than 1V. The 5礎 pull-down current source and the
15礎 pull-up current source are designed low enough in
value so that an external resistor divider network can drive
the SHDN pin to provide overvoltage protection or to
provide thermal shutdown with the use of a thermistor in
the divider network. Diode-ORing these functions to-
gether is simple to accomplish and provides multiple
functionality for one pin.
If the current limit amplifier is not used, two choices
present themselves. The simplest choice is to tie the INEG
pin directly to the IPOS pin. This action defeats current
limit and provides the simplest, no frills circuit. An appli-
cation in which the current limit amplifier is not used is
where an extremely low dropout voltage must be achieved
and the 50mV threshold voltage cannot be tolerated.
However, a second available choice permits a user to
provide short-circuit protection with no external sensing.
This technique is activated by grounding the INEG pin.
This action disables the current limit amplifier because
Schottky diode D1 clamps the amplifiers output and
prevents Q2 from pulling down the COMP node. In addi-
tion, Schottky diode D2 turns off pull-down transistor Q1.
Q1 is normally on and holds internal comparator COMP3s
output low. This comparator circuit, now enabled, moni-
tors the GATE pin and detects saturation at the positive rail.
When a saturated condition is detected, COMP3 activates
the shutdown timer. Once the time-out period occurs, the
output is shut down and latched off. The operation of
resetting the latch remains the same. Note that this tech-
nique does not limit the FET current during the time-out
period. The output current is only limited by the input
power supply and the input/output impedance. Setting the
timer to a short period in this mode of operation keeps the
external MOSFET within its SOA (safe operating area)
boundary and keeps the MOSFETs temperature rise under
control.
Unique circuit design incorporated into the LT1575 allevi-
ates all concerns about power supply sequencing. The
issue of power supply sequencing is an important topic as
the typical LT1575 application has inputs from two sepa-
rate power supply voltages. If the typical 12V V
IN
supply
voltage is slow in ramping up, insufficient MOSFET gate
drive is present and therefore, the output voltage does
not come up. If the V
IN
supply voltage is present, but the
typical 5V supply voltage tied to the IPOS pin has not
started yet, then the feedback loop wants to drive the
GATE pin to the positive V
IN
rail. This would result in a
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