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| 型号： | LT1575CS8-3.3 |
| 厂商： | Linear Technology |
| 文件页数： | 3/20页 |
| 文件大小： | 312K |
| 描述： | IC REG CTRLR SGL 3.3V 8SOIC |
| 标准包装： | 100 |
| 类型： | 正，固定式 |
| 输出数： | 1 |
| 输出电压： | 3.3V |
| 电流 - 电源： | 12mA |
| 输入电压： | 10 V ~ 20 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 管件 |
3
LT1575/LT1577
ELECTRICAL CHARACTERISTICS
T
A
= 25?/SPAN>C, V
IN
= 12V, GATE = 6V, IPOS = INEG = 5V, SHDN = 0.75V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Q
Supply Current
q
5
12
19
mA
V
FB
LT1575 Reference Voltage
0.6
1.210
0.6
%
q
1.0
1.210
1.0
%
V
OUT
LT1575-1.5 Output Voltage
0.6
1.500
0.6
%
q
1.0
1.500
1.0
%
LT1575-2.8 Output Voltage
0.6
2.800
0.6
%
q
1.0
2.800
1.0
%
LT1575-3.3 Output Voltage
0.6
3.300
0.6
%
q
1.0
3.300
1.0
%
LT1575-3.5 Output Voltage
0.6
3.500
0.6
%
q
1.0
3.500
1.0
%
LT1575-5 Output Voltage
0.6
5.000
0.6
%
q
1.0
5.000
1.0
%
Line Regulation
10V d V
IN
d 20V
q
0.01
0.03
%/V
I
FB
FB Input Bias Current
FB = V
FB
q
0.6
4.0
礎
I
OUT
OUT Divider Current
OUT = V
OUT
q
0.5
1.0
1.5
mA
A
VOL
LT1575 Large-Signal Voltage Gain
V
GATE
= 3V to 10V
q
69
84
dB
LT1575-1.5 Large-Signal Voltage Gain
V
GATE
= 3V to 10V
q
67
82
dB
LT1575-2.8 Large-Signal Voltage Gain
V
GATE
= 3V to 10V
q
60
76
dB
LT1575-3.3 Large-Signal Voltage Gain
V
GATE
= 3V to 10V
q
60
75
dB
LT1575-3.5 Large-Signal Voltage Gain
V
GATE
= 3V to 10V
q
60
74
dB
LT1575-5 Large-Signal Voltage Gain
V
GATE
= 3V to 10V
q
56
71
dB
V
OL
GATE Output Swing Low (Note 3)
I
GATE
= 0mA
q
2.5
3.0
V
V
OH
GATE Output Swing High
I
GATE
= 0mA
q
V
IN
1.6
V
IN
1
V
IPOS + INEG Supply Current
3V d IPOS d 20V
q
0.3
0.625
1.0
mA
Current Limit Threshold Voltage
42
50
58
mV
q
37
50
63
mV
Current Limit Threshold Voltage
3V d IPOS d 20V
q
0.20
0.50
%/V
Line Regulation
SHDN Sink Current
Current Flows Into Pin
q
2.5
5.0
8.0
礎
SHDN Source Current
Current Flows Out of Pin
q
8
15
23
礎
SHDN Low Clamp Voltage
q
0.1
0.25
V
SHDN High Clamp Voltage
q
1.50
1.85
2.20
V
SHDN Threshold Voltage
q
1.18
1.21
1.240
V
SHDN Threshold Hysteresis
q
50
100
150
mV
The q denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formulas:
LT1575CN8: T
J
= T
A
+ (P
D
" 100癈W)
LT1575CS8: T
J
= T
A
+ (P
D
" 130癈W)
LT1577CS: T
J
= T
A
+ (P
D
" 100癈W)
Because the LT1577 consists of two regulators in the package, the total
LT1577 power dissipation must be used for its junction temperature
calculation. The total LT1577 P
D
= P
D
(Regulator 1) + P
D
(Regulator 2).
Note 3: The V
GS(th)
of the external MOSFET must be greater than
3V V
OUT
.
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