参数资料
型号: LT1578CS8-2.5#TRPBF
厂商: Linear Technology
文件页数: 21/28页
文件大小: 0K
描述: IC REG BUCK 2.5V 1.5A 8SOIC
标准包装: 2,500
类型: 降压(降压)
输出类型: 固定
输出数: 1
输出电压: 2.5V
输入电压: 4 V ~ 15 V
PWM 型: 电流模式
频率 - 开关: 200kHz
电流 - 输出: 1.5A
同步整流器:
工作温度: 0°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
供应商设备封装: 8-SOIC
LT1578/LT1578-2.5
APPLICATIO N S I N FOR M ATIO N
( R C )( G MA ) ( V IN ? V OUT )( ESR )( 1 . 21 )
( )
( V IN )( L )( f )
( = 15 k ) ( ) 3 ? ( )( )( ) = 0 . 151 V
( ) ( )( ) 3
) ( G MP )( G MA )( )( )
(
R C Loop Gain = 1 =
Analog experts will note that around 7kHz, phase dips
close to the zero phase margin line. This is typical of
switching regulators, especially those that operate over a
wide range of loads. This region of low phase is not a
problem as long as it does not occur near unity-gain. In
practice, the variability of output capacitor ESR tends to
dominate all other effects with respect to loop response.
Variations in ESR will cause unity-gain to move around,
but at the same time phase moves with it so that adequate
phase margin is maintained over a very wide range of ESR
( ≥ ± 3:1).
What About a Resistor in the Compensation Network?
It is common practice in switching regulator design to add
a “zero” to the error amplifier compensation to increase
loop phase margin. This zero is created in the external
network in the form of a resistor (R C ) in series with the
compensation capacitor. Increasing the size of this resis-
tor generally creates better and better loop stability, but
there are two limitations on its value. First, the combina-
tion of output capacitor ESR and a large value for R C may
cause loop gain to stop rolling off altogether, creating a
gain margin problem. An approximate formula for R C
where gain margin falls to zero is:
V OUT
ESR 1 . 21
G MP = Transconductance of power stage = 1.5A/V
G MA = Error amplifier transconductance = 1(10 –3 )
ESR = Output capacitor ESR
1.21 = Reference voltage
With V OUT = 5V and ESR = 0.1 ? , a value of 27.5k for R C
would yield zero gain margin, so this represents an upper
limit. There is a second limitation however which has
nothing to do with theoretical small signal dynamics. This
resistor sets high frequency gain of the error amplifier,
evidenced by alternating pulse widths seen at the switch
node. In more severe cases, the regulator squeals or
hisses audibly even though the output voltage is still
roughly correct. None of this will show on a Bode plot
since this is an amplitude insensitive measurement. Tests
have shown that if ripple voltage on the V C is held to less
than 100mV P-P , the LT1578 will generally be well behaved.
The formula below will give an estimate of V C ripple
voltage when R C is added to the loop, assuming that R C is
large compared to the reactance of C C at 200kHz.
V C RIPPLE =
G MA = Error amplifier transconductance (1000 μ Mho)
If a series compensation resistor of 15k gave the best
overall loop response, with adequate gain margin, the
resulting V C pin ripple voltage with V IN = 10V, V OUT = 5V,
ESR = 0.1 ? , L = 30 μ H, would be:
1 ? 10 10 ? 5 0 . 1 1 . 21
V C ( RIPPLE ) 10 30 ? 10 ? 6 200 ? 10
This ripple voltage is high enough to possibly create
subharmonic switching. In most situations a compromise
value (< 10k in this case) for the resistor gives acceptable
phase margin and no subharmonic problems. In other
cases, the resistor may have to be larger to get acceptable
phase response, and some means must be used to control
ripple voltage at the V C pin. The suggested way to do this
is to add a capacitor (C F ) in parallel with the R C /C C network
on the V C pin. The pole frequency for this capacitor is
typically set at one-fifth of the switching frequency so that
it provides significant attenuation of the switching ripple,
but does not add unacceptable phase shift at the loop
unity-gain frequency. With R C = 15k,
(
) ( )
2 π 200 ? 10 15 k
including  the  gain  at  the  switching  frequency.  If  the
switching frequency gain is high enough, an excessive
amout of output ripple voltage will appear at the V C pin
resulting in improper operation of the regulator. In a
C F =
5
( 2 π )( f )( R C )
=
5
3
= 265 pF
marginal case, subharmonic switching occurs, as
21
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