参数资料
型号: LT1613CS5#TRM
厂商: Linear Technology
文件页数: 4/12页
文件大小: 0K
描述: IC REG BST FLYBACK SEPIC TSOT23
标准包装: 1
类型: 升压(升压),回扫,Sepic
输出类型: 可调式
输出数: 1
输出电压: 1.23 V ~ 36 V
输入电压: 1.1 V ~ 10 V
PWM 型: 电流模式
频率 - 开关: 1.4MHz
电流 - 输出: 300mA
同步整流器:
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: SOT-23-5 细型,TSOT-23-5
包装: 剪切带 (CT)
供应商设备封装: TSOT-23-5
其它名称: LT1613CS5
LT1613CS5#TRMCT
LT1613CS5-ND
LT1613
PI N FU N CTIO N S
SW (Pin 1): Switch Pin. Connect inductor/diode here.
Minimize trace area at this pin to keep EMI down.
GND (Pin 2): Ground. Tie directly to local ground plane.
FB (Pin 3): Feedback Pin. Reference voltage is 1.23V.
Connect resistive divider tap here. Minimize trace area at
FB. Set V OUT according to V OUT = 1.23V(1 + R1/R2).
BLOCK DIAGRA M
SHDN (Pin 4): Shutdown Pin. Tie to 1V or more to enable
device. Ground to shut down.
V IN (Pin 5): Input Supply Pin. Must be locally bypassed.
V IN 5
R5
R6
V IN
V OUT
40k
40k
+
COMPARATOR
1 SW
R1
(EXTERNAL)
FB
FB 3
Q1
Q2
x10
A1
g m
R C
C C
RAMP
GENERATOR
Σ
A2
R
FF
S
Q
DRIVER
+
Q3
R2
(EXTERNAL)
R3
30k
0.15 ?
R4
140k
1.4MHz
OSCILLATOR
SHDN
4
SHUTDOWN
2 GND
1613 ? BD
OPERATIO
The LT1613 is a current mode, internally compensated,
fixed frequency step-up switching regulator. Operation
can be best understood by referring to the Block Diagram.
Q1 and Q2 form a bandgap reference core whose loop is
closed around the output of the regulator. The voltage
drop across R5 and R6 is low enough such that Q1 and Q2
do not saturate, even when V IN is 1V. When there is no
load, FB rises slightly above 1.23V, causing V C (the error
amplifier’s output) to decrease. Comparator A2’s output
stays high, keeping switch Q3 in the off state. As increased
output loading causes the FB voltage to decrease, A1’s
output increases. Switch current is regulated directly on a
cycle-by-cycle basis by the V C node. The flip flop is set at
the beginning of each switch cycle, turning on the switch.
When the summation of a signal representing switch
current and a ramp generator (introduced to avoid
4
subharmonic oscillations at duty factors greater than
50%) exceeds the V C signal, comparator A2 changes
state, resetting the flip flop and turning off the switch.
More power is delivered to the output as switch current is
increased. The output voltage, attenuated by external
resistor divider R1 and R2, appears at the FB pin, closing
the overall loop. Frequency compensation is provided
internally by R C and C C . Transient response can be opti-
mized by the addition of a phase lead capacitor C PL in
parallel with R1 in applications where large value or low
ESR output capacitors are used.
As the load current is decreased, the switch turns on for a
shorter period each cycle. If the load current is further
decreased, the converter will skip cycles to maintain
output voltage regulation.
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