参数资料
| 型号： | LT1613CS5#TRM |
| 厂商： | Linear Technology |
| 文件页数： | 5/12页 |
| 文件大小： | 0K |
| 描述： | IC REG BST FLYBACK SEPIC TSOT23 |
| 标准包装： | 1 |
| 类型： | 升压（升压），回扫，Sepic |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1.23 V ~ 36 V |
| 输入电压： | 1.1 V ~ 10 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1.4MHz |
| 电流 - 输出： | 300mA |
| 同步整流器： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-5 细型，TSOT-23-5 |
| 包装： | 剪切带 (CT) |
| 供应商设备封装： | TSOT-23-5 |
| 其它名称： | LT1613CS5 LT1613CS5#TRMCT LT1613CS5-ND |
LT1613
OPERATIO
LAYOUT
The LT1613 switches current at high speed, mandating
V IN
4V TO
7V
L1A
22 μ H
C3
1 μ F
careful attention to layout for proper performance. You
will not get advertised performance with careless layouts.
+
C1
15 μ F
V IN
LT1613
SW
R1
L1B
22 μ H
D1
Figure 2 shows recommended component placement for
a boost (step-up) converter. Follow this closely in your
SHDN
SHDN
GND
FB
100k
R2
32.4k
+
V OUT
5V/150mA
C2
15 μ F
PCB layout. Note the direct path of the switching loops.
Input capacitor C1 must be placed close (< 5mm) to the IC
C1, C2: AVX TAJA156M016
C3: TAIYO YUDEN JMK325BJ226MM
D1: MOTOROLA MBR0520
package. As little as 10mm of wire or PC trace from C IN to
L1, L2: MURATA LQH3C220
1613 F03
V IN will cause problems such as inability to regulate or
oscillation.
The ground terminal of output capacitor C2 should tie
close to Pin 2 of the LT1613. Doing this reduces dI/dt in the
ground copper which keeps high frequency spikes to a
minimum. The DC/DC converter ground should tie to the
Figure 3. Single-Ended Primary Inductance Converter (SEPIC)
Generates 5V from An Input Voltage Above or Below 5V
PC board ground plane at one place only, to avoid intro-
ducing dI/dt in the ground plane.
A SEPIC (single-ended primary inductance converter)
schematic is shown in Figure 3. This converter topology
V OUT
+
D1
C2
L1B
C3
L1A
1
+
C1
5
V IN
produces a regulated output voltage that spans (i.e., can
2
be higher or lower than) the output. Recommended com-
ponent placement for a SEPIC is shown in Figure 4.
VIAS TO
GROUND
3
4
SHUTDOWN
PLANE
R2
L1
+
GROUND
R1
1613 F04
C1
V IN
V OUT
D1
Figure 4. Recommended Component Placement for SEPIC
+
C2
1
5
COMPONENT SELECTION
2
VIAS TO
GROUND
PLANE
3
R2
4
SHUTDOWN
Inductors
Inductors used with the LT1613 should have a saturation
current rating (where inductance is approximately 70% of
GROUND
R1
1613 F02
Figure 2. Recommended Component Placement for Boost
Converter. Note Direct High Current Paths Using Wide PCB
Traces. Minimize Area at Pin 3 (FB). Use Vias to Tie Local
Ground Into System Ground Plane. Use Vias at Location Shown
to Avoid Introducing Switching Currents Into Ground Plane
zero current inductance) of approximately 0.5A or greater.
DCR of the inductors should be 0.5 ? or less. For boost
converters, inductance should be 4.7 μ H for input voltage
less than 3.3V and 10 μ H for inputs above 3.3V. When
using the device as a SEPIC, either a coupled inductor or
two separate inductors can be used. If using separate
inductors, 22 μ H units are recommended for input voltage
above 3.3V. Coupled inductors have a beneficial mutual
inductance, so a 10 μ H coupled inductor results in the
same ripple current as two 20 μ H uncoupled units.
5
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