参数资料
| 型号： | LT1680ISW#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 6/16页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST PWM CM 16-SOIC |
| 标准包装： | 47 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 200kHz |
| 占空比： | 90% |
| 电源电压： | 4 V ~ 60 V |
| 降压： | 无 |
| 升压： | 是 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 包装： | 管件 |
| 产品目录页面： | 1328 (CN2011-ZH PDF) |
LT1680
TYPICAL PERFOR A CE CHARACTERISTICS
RUN/SHDN Input Current
Operating Frequency
600
vs Pin Voltage
100
Maximum Duty Cycle vs R CT
1.01
(Normalized) vs Temperature
450
FULL OPERATING
TEMPERATURE
RANGE
UPPER
LIMIT
90
80
70
I DISCHG = 2.75mA
1.00
60
300
TYPICAL
50
150
LOWER
LIMIT
40
30
20
10
I DISCHG = 2.1mA
FULL OPERATING
TEMPERATURE
RANGE
0.99
0
0
2
4 6 8
10
12
0
1
2
4
6
10 20
40 60 100
0.98
–50 –25
0
25
50
75
100
125
RUN/SHDN PIN VOLTAGE (V)
PI FU CTIO S
1680 G19
R CT (k ? )
1680 G20
TEMPERATURE ( ° C)
1680 G21
SL/ADJ (Pin 1): Slope Compensation Adjustment. Allows
increased slope compensation for certain high duty cycle
applications. Resistive loading of this pin increases effec-
tive slope compensation. A resistor divider from the 5V REF
pin can tailor the onset of additional slope compensation
to specific regions in each switch cycle. Pin can be floated
or connected to 5V REF if no additional slope compensation
is required. (See Applications Information section for
slope compensation details.)
C T (Pin 2): Oscillator Timing Pin. Connect a capacitor
(C CT ) to ground and a pull-up resistor (R CT ) to the 5V REF
supply. Typical values are C CT = 1000pF and 10k ≤ R CT ≤
30k.
I AVG (Pin 3): Average Current Limit Integration. The
frequency response characteristic is set using 50k ?
output impedance of this pin and external capacitor. The
external capacitor is typically connected from the I AVG pin
to the V C pin, but can also be connected from the I AVG pin
to ground. Connecting the capacitor from the I AVG pin to
the V C pin uses an internal gain block to form an active
integrator, minimizing the capacitance required for stable
operation. A typical value for this integration capacitor is
220pF from I AVG to V C . Shorting this pin to SGND will
disable the average current limit function.
6
SS (Pin 4): Soft Start. Generates ramping threshold for
regulator current limit during start-up and after UVLO
events by sourcing about 8 μ A into an external capacitor.
V C (Pin 5): Error Amplifier Output. RC load creates domi-
nant compensation in power supply regulation feedback
loop to provide optimum transient response. (See Appli-
cations Information section for compensation details.)
SGND (Pin 6): Small-Signal Ground. Connect to negative
terminal of C OUT .
V FB (Pin 7): Error Amplifier Inverting Input. Used as
voltage feedback input node for regulator loop. Pin sources
about 0.5 μ A DC bias current to protect from an open
feedback path condition.
V REF (Pin 8): Bandgap Generated Voltage Reference
Decoupling. Connect a capacitor to signal ground. (Typi-
cal capacitor value ≈ 0.1 μ F.)
SENSE + (Pin 9): Current Sense Amplifier Inverting Input.
Connect to most positive (DC) terminal of current sense
resistor.
SENSE – (Pin 10): Current Sense Amplifier Noninverting
Input. Connect to most negative (DC) terminal of current
sense resistor.
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