参数资料
| 型号： | LT1683EG#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 7/26页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR PWM CM 20-SSOP |
| 标准包装： | 66 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 250kHz |
| 占空比： | 46% |
| 电源电压： | 4 V ~ 20 V |
| 降压： | 无 |
| 升压： | 是 |
| 回扫： | 是 |
| 反相： | 是 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 20-SSOP（0.209"，5.30mm 宽） |
| 包装： | 管件 |
| 产品目录页面： | 1328 (CN2011-ZH PDF) |
LT1683
PIN FUNCTIONS
should be set close to the external clock frequency. Syn-
chronizing the clock to an external reference is useful for
creating more stable positioning of the switcher voltage
and current harmonics. This pin can be left open or tied
to ground if not used.
C T (Pin 7): The oscillator capacitor pin is used in conjunc-
tion with R T to set the oscillator frequency. For R T = 16.9k:
C OSC (nf) = 129/f OSC (kHz)
R T (Pin 8): The oscillator resistor pin is used to set the
charge and discharge currents of the oscillator capacitor.
The nominal value is 16.9k. It is possible to adjust this re-
sistance ±25% to set oscillator frequency more accurately.
Gate Drive
GATE A, GATE B (Pins 1, 19): These pins connect to the
gates of the external N-channel MOSFETs. GATE A and
GATE B turn on with alternate clock cycles. These drivers
are capable of sinking and sourcing at least 300mA.
The GCL pin sets the upper voltage of the gate drive. The
gate pins will not be activated until V IN reaches a minimum
voltage as defined by the GCL pin (gate undervoltage
lockout).
The gate drive outputs have current limit protection to
safe guard against accidental shorts.
If the gate drive voltage is greater than about 1V the
opposite gate drive is inhibited thus preventing cross
conduction.
GCL (Pin 3): This pin sets the maximum gate voltage to
the GATE A and GATE B pins to the MOSFET gate drives.
This pin should be either tied to a Zener, a voltage source
or V IN .
If the pin is tied to a Zener or a voltage source, the
maximum gate drive voltage will be approximately
V GCL – 0.2V. If it is tied to V IN , the maximum gate voltage
is approximately V IN – 1.6.
Approximately 50μA of current can be sourced from this
pin if V GCL < V IN – 0.8V.
This pin also controls undervoltage lockout of the gate
drives. If the pin is tied to a Zener or voltage source, the
gate drive will not be enabled until V IN > V GCL + 0.8V. If this
pin is tied to V IN , then undervoltage lockout is disabled.
There is an internal 19V Zener tied from this pin to ground
to provide a fail-safe for maximum gate voltage.
Slew Control
CAP A, CAP B (Pins 2, 18): These pins are the feedback
nodes for the external voltage slewing capacitors. Normally
a small 1pf to 5pf capacitor is connected from this pin to
the drain of its respective MOSFET.
The voltage slew rate is inversely proportional to this
capacitance and proportional to the current that the part
will sink and source on this pin. That current is inversely
proportional to R VSL .
R CSL (Pin 15): A resistor to ground sets the current slew
rate for the external drive MOSFETs during switching. The
minimum resistor value is 3.3k and the maximum value
is 68k. The time to slew between on and off states of
the MOSFET current will determine how the di/dt related
harmonics are reduced. This time is proportional to R CSL
and R S (the current sense resistor) and maximum cur-
rent. Longer times produce a greater reduction of higher
frequency harmonics.
R VSL (Pin 16): A resistor to ground sets the voltage slew
rate for the drains of the external drive MOSFETs. The
minimum resistor value is 3.3k and the maximum value
is 68k. The time to slew between on and off states on the
MOSFET drain voltage will determine how harmonics are
reduced from this source. This time is proportional to R VSL ,
C VA/B and the input voltage. Longer times produce more
rolloff of harmonics. C VA/B is the equivalent capacitance
from CAP A or B to the drain of the MOSFET.
Switch Mode Control
CS (Pin 4): This is the input to the current sense amplifier.
It is used for both current mode control and current slewing
of the external MOSFETs. Current sense is accomplished
via a sense resistor (R S ) connected from the sources of
the external MOSFETs to ground. CS is connected to the
top of R S . Current sense is referenced to the GND pin.
1683fd
7
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LT1683IG | 功能描述:IC REG CTRLR PWM CM 20-SSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,500 系列:PowerWise® PWM 型:控制器 输出数:1 频率 - 最大:1MHz 占空比:95% 电源电压:2.8 V ~ 5.5 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:6-WDFN 裸露焊盘 包装:带卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名称:LM1771SSDX |
| LT1683IG#PBF | 功能描述:IC REG CTRLR PWM CM 20-SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,500 系列:PowerWise® PWM 型:控制器 输出数:1 频率 - 最大:1MHz 占空比:95% 电源电压:2.8 V ~ 5.5 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:6-WDFN 裸露焊盘 包装:带卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名称:LM1771SSDX |
| LT1683IG#TR | 功能描述:IC REG CTRLR PWM CM 20-SSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,500 系列:PowerWise® PWM 型:控制器 输出数:1 频率 - 最大:1MHz 占空比:95% 电源电压:2.8 V ~ 5.5 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:6-WDFN 裸露焊盘 包装:带卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名称:LM1771SSDX |
| LT1683IG#TRPBF | 功能描述:IC REG CTRLR PWM CM 20-SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,500 系列:PowerWise® PWM 型:控制器 输出数:1 频率 - 最大:1MHz 占空比:95% 电源电压:2.8 V ~ 5.5 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:6-WDFN 裸露焊盘 包装:带卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名称:LM1771SSDX |
| LT1684 | 制造商:LINER 制造商全称:Linear Technology 功能描述:Micropower Ring Tone Generator |
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