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| 型号： | LT1719CS8 |
| 厂商： | Linear Technology |
| 文件页数： | 7/22页 |
| 文件大小： | 0K |
| 描述： | IC COMP R-R I/O SGL 3/5V 8-SOIC |
| 标准包装： | 100 |
| 系列： | UltraFast™ |
| 类型： | 通用 |
| 元件数： | 1 |
| 输出类型： | CMOS，满摆幅，TTL |
| 电压 - 电源，单路/双路(±)： | 2.7 V ~ 6 V |
| 电压 - 输入偏移（最小值）： | 2.5mV @ ±5V |
| 电流 - 输入偏压（最小值）： | 6µA @ ±5V |
| 电流 - 输出（标准）： | 20mA |
| 电流 - 静态（最大值）： | 9mA |
| CMRR, PSRR（标准）： | 70dB CMRR，80dB PSRR |
| 传输延迟（最大）： | 4.2ns |
| 磁滞： | 7mV |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 安装类型： | 表面贴装 |
| 包装： | 管件 |
| 其它名称： | Q1357287 |
LT1719
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1719fa
Figure 6b shows a three resistor level translator for inter-
facing the LT1719 to ECL running off the same supply rail.
No pull-down on the output of the LT1719 is needed, but
pull-down R3 limits the VIH seen by the PECL gate. This
is needed because ECL inputs have both a minimum and
maximum VIH specication for proper operation. Resis-
tor values are given for both ECL interface types; in both
cases it is assumed that the LT1719 operates from the
same supply rail.
Figure 6c shows the case of translating to PECL from
an LT1719 powered by a 3V supply rail. Again, resistor
values are given for both ECL interface types. This time
four resistors are needed, although with 10KH/E, R3 is not
needed. In that case, the circuit resembles the standard
TTL translator of Figure 6a, but the function of the new
resistor, R4, is much different. R4 loads the LT1719 output
when high so that the current owing through R1 doesn’t
forward bias the LT1719’s internal ESD clamp diode.
Although this diode can handle 20mA without damage,
normal operation and performance of the output stage can
be impaired above 100μA of forward current. R4 prevents
this with the minimum additional power dissipation.
Finally, Figure 6d shows the case of driving standard,
negative-rail, ECL with the LT1719. Resistor values are
given for both ECL interface types and for both a 5V
and 3V LT1719 supply rail. Again, a fourth resistor, R4
is needed to prevent the low state current from owing
out of the LT1719, turning on the internal ESD/substrate
diodes. Resistor R4 again prevents this with the minimum
additional power dissipation.
Of course, in the SO-8 package, if the VEE of the LT1719
is the same as the ECL negative supply, the GND pin can
be tied to it as well and + VS grounded. Then the output
stage has the same power rails as the ECL and the circuits
of Figure 6b can be used.
For all the dividers shown, the output impedance is about
110Ω. This makes these fast, less than a nanosecond,
with most layouts. Avoid the temptation to use speedup
capacitors. Not only can they foul up the operation of the
ECL gate because of overshoots, they can damage the ECL
inputs, particularly during power-up of separate supply
congurations.
Similar circuits can be used with the emerging LVECL and
LVPECL standards.
The level translator designs shown assume one gate
load. Multiple gates can have signicant IIH loading, and
the transmission line routing and termination issues also
make this case difcult.
ECL, and particularly PECL, is valuable technology for high
speed system design, but it must be used with care. With
less than a volt of swing, the noise margins need to be
evaluated carefully. Note that there is some degradation of
noise margin due to the ±5% resistor selections shown.
With 10KH/E, there is no temperature compensation of
the logic levels, whereas the LT1719 and the circuits
shown give levels that are stable with temperature. This
will lower the noise margin over temperature. In some
congurations it is possible to add compensation with
diode or transistor junctions in series with the resistors
of these networks.
For more information on ECL design, refer to the ECLiPS
data book (DL140), the 10KH system design handbook
(HB205) and PECL design (AN1406), all from Motorola,
now ON Semiconductor.
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| LT1719CS8#PBF | 功能描述:IC COMP R-R I/O SGL 3/5V 8-SOIC RoHS:是 类别:集成电路 (IC) >> 线性 - 比较器 系列:UltraFast™ 标准包装:1 系列:- 类型:通用 元件数:1 输出类型:CMOS，开路集电极，TTL 电压 - 电源，单路/双路(±):2.7 V ~ 5.5 V 电压 - 输入偏移（最小值）:7mV @ 5V 电流 - 输入偏压（最小值）:0.25µA @ 5V 电流 - 输出（标准）:84mA @ 5V 电流 - 静态（最大值）:120µA CMRR, PSRR（标准）:- 传输延迟（最大）:600ns 磁滞:- 工作温度:-40°C ~ 85°C 封装/外壳:SC-74A，SOT-753 安装类型:表面贴装 包装:剪切带 (CT) 产品目录页面:1268 (CN2011-ZH PDF) 其它名称:*LMV331M5*LMV331M5/NOPBLMV331M5CT |
| LT1719CS8#TR | 功能描述:IC COMP R-R SINGLE 4.5NS 8SOIC RoHS:否 类别:集成电路 (IC) >> 线性 - 比较器 系列:UltraFast™ 标准包装:25 系列:- 类型:带电压基准 元件数:4 输出类型:CMOS，开路漏极，TTL 电压 - 电源，单路/双路(±):2 V ~ 11 V，±1 V ~ 5.5 V 电压 - 输入偏移（最小值）:10mV @ 5V 电流 - 输入偏压（最小值）:- 电流 - 输出（标准）:0.015mA @ 5V 电流 - 静态（最大值）:8.5µA CMRR, PSRR（标准）:80dB CMRR，80dB PSRR 传输延迟（最大）:12µs 磁滞:50mV 工作温度:0°C ~ 70°C 封装/外壳:16-DIP（0.300"，7.62mm） 安装类型:通孔 包装:管件 |
| LT1719CS8#TRPBF | 功能描述:IC COMP R-R I/O SGL 3/5V 8-SOIC RoHS:是 类别:集成电路 (IC) >> 线性 - 比较器 系列:UltraFast™ 标准包装:25 系列:- 类型:带电压基准 元件数:4 输出类型:CMOS，开路漏极，TTL 电压 - 电源，单路/双路(±):2 V ~ 11 V，±1 V ~ 5.5 V 电压 - 输入偏移（最小值）:10mV @ 5V 电流 - 输入偏压（最小值）:- 电流 - 输出（标准）:0.015mA @ 5V 电流 - 静态（最大值）:8.5µA CMRR, PSRR（标准）:80dB CMRR，80dB PSRR 传输延迟（最大）:12µs 磁滞:50mV 工作温度:0°C ~ 70°C 封装/外壳:16-DIP（0.300"，7.62mm） 安装类型:通孔 包装:管件 |
| LT1719CS8PBF | 制造商:Linear Technology 功能描述:LT1719 4.5ns LP SOIC comparator |
| LT1719IS6 | 制造商:Linear Technology 功能描述:Comparator Single R-R O/P |
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