参数资料
型号: LT1719IS8#TRPBF
厂商: Linear Technology
文件页数: 4/22页
文件大小: 0K
描述: IC COMP R-RINOUT SINGLE 8-SOIC
标准包装: 2,500
系列: UltraFast™
类型: 通用
元件数: 1
输出类型: CMOS,满摆幅,TTL
电压 - 电源,单路/双路(±): 2.7 V ~ 6 V
电压 - 输入偏移(最小值): 2.5mV @ ±5V
电流 - 输入偏压(最小值): 6µA @ ±5V
电流 - 输出(标准): 20mA
电流 - 静态(最大值): 9mA
CMRR, PSRR(标准): 70dB CMRR,80dB PSRR
传输延迟(最大): 4.2ns
磁滞: 7mV
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
安装类型: 表面贴装
包装: 带卷 (TR)
LT1719
12
1719fa
on the common mode and power supply dependence of
the hysteresis voltage.
Additional hysteresis may be added externally. The rail-
to-rail outputs of the LT1719 make this more predictable
than with TTL output comparators due to the LT1719’s
small variability of VOH (output high voltage).
To add additional hysteresis, set up positive feedback
by adding additional external resistor R3 as shown in
Figure 4. Resistor R3 adds a portion of the output to the
threshold set by the resistor string. The LT1719 pulls the
outputs to + VS and ground to within 200mV of the rails
with light loads, and to within 400mV with heavy loads.
For the load of most circuits, a good model for the voltage
on the right side of R3 is 300mV or +VS – 300mV, for a
total voltage swing of (+VS – 300mV) – (300mV) = +VS
– 600mV.
The exact amount of hysteresis will vary from part to part
as indicated in the specications table. The hysteresis level
will also vary slightly with changes in supply voltage and
common mode voltage. A key advantage of the LT1719
is the signicant reduction in these effects, which is im-
portant whenever an LT1719 is used to detect a threshold
crossing in one direction only. In such a case, the relevant
trip point will be all that matters, and a stable offset volt-
age with an unpredictable level of hysteresis, as seen in
competing comparators, is useless. The LT1719 is many
times better than prior comparators in these regards. In
fact, the CMRR and PSRR tests are performed by check-
ing for changes in either trip point to the limits indicated
in the specications table. Because the offset voltage is
the average of the trip points, the CMRR and PSRR of the
offset voltage is therefore guaranteed to be at least as good
as those limits. This more stringent test also puts a limit
+
LT1719S8
INPUT
1719 F04
R2
VREF
R3
R1
Figure 4. Additional External Hysteresis
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