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| 型号： | LT1720IMS8#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/28页 |
| 文件大小： | 0K |
| 描述： | IC COMPARATOR DUAL HS 3/5V 8MSOP |
| 标准包装： | 50 |
| 系列： | UltraFast™ |
| 类型： | 通用 |
| 元件数： | 2 |
| 输出类型： | CMOS，满摆幅，TTL |
| 电压 - 电源，单路/双路(±)： | 2.7 V ~ 6 V |
| 电压 - 输入偏移（最小值）： | 3mV @ 5V |
| 电流 - 输入偏压（最小值）： | 6µA @ 5V |
| 电流 - 输出（标准）： | 20mA |
| 电流 - 静态（最大值）： | 7mA |
| CMRR, PSRR（标准）： | 70dB CMRR，80dB PSRR |
| 传输延迟（最大）： | 10ns |
| 磁滞： | 7mV |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 安装类型： | 表面贴装 |
| 包装： | 管件 |
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LT1720/LT1721
17
17201fc
Timing Skews
For a number of reasons, the LT1720/LT1721’s superior
timing specications make them an excellent choice for
applications requiring accurate differential timing skew.
The comparators in a single package are inherently well
matched, with just 300ps
ΔtPDtypical.Monolithicconstruc-
tion keeps the delays well matched vs supply voltage and
temperature. Crosstalk between the comparators, usually a
disadvantage in monolithic duals and quads, has minimal
effect on the LT1720/LT1721 timing due to the internal
hysteresis, as described in the Speed Limits section.
The circuits of Figure 11 show basic building blocks for
differential timing skews. The 2.5k resistance interacts with
the 2pF typical input capacitance to create at least
±4ns
delay, controlled by the potentiometer setting. A differential
and a single-ended version are shown. In the differential
conguration, the output edges can be smoothly scrolled
through
Δt = 0 with negligible interaction.
3ns Delay Detector
It is often necessary to measure comparative timing of
pulse edges in order to determine the true synchronicity
of clock and control signals, whether in digital circuitry
or in high speed instrumentation. The circuit in Figure 12
APPLICATIONS INFORMATION
is a delay detector which will output a pulse when signals
X and Y are out of sync (specically, when X is high and
Y is low). Note that the addition of an identical circuit to
detect the opposite situation (X low and Y high) allows
for full skew detection.
Comparators U1A and U1B clean up the incoming signals
and render the circuit less sensitive to input levels and
slew rates. The resistive divider network provides level
shifting for the downstream comparator’s common mode
input range, as well as offset to keep the output low except
during a decisive event. When the upstream comparator’s
outputs can overcome the resistively generated offset (and
hysteresis), comparator U1C performs a Boolean “X*_Y”
function and produces an output pulse (see Figure 13).
The circuit will give full output response with input delays
down to 3ns and partial output response with input delays
down to 1.8ns. Capacitor C1 helps ensure that an imbal-
ance of parasitic capacitances in the layout will not cause
common mode excursions to result in differential mode
signal and false outputs.1
1 Make sure the input levels at X and Y are not too close to the 0.5V threshold set by the R8–R9
divider. If you are still getting false outputs, try increasing C1 to 10pF or more. You can also look
for the problem in the impedance balance (R5 || R6 = R7) at the inputs of U1C. Increasing the
offset by lowering R5 will help reject false outputs, but R7 should also be lowered to maintain
impedance balance. For ease of design and parasitic matching, R7 can be replaced by two parallel
resistors equal to R5 and R6.
LT1720
DIFFERENTIAL 4ns
RELATIVE SKEW
CIN
VREF
2.5k
INPUT
LT1720
0ns TO 4ns
SINGLE-ENDED
DELAY
CIN
17201 F11
VREF
INPUT
CIN
–
+
–
+
–
+
–
+
Figure 11. Building Blocks for Timing Skew Generation with the LT1720
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相关代理商/技术参数 |
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|---|---|
| LT1720IS8 | 功能描述:IC COMP R-RINOUT DUAL 8-SOIC RoHS:否 类别:集成电路 (IC) >> 线性 - 比较器 系列:UltraFast™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:通用 元件数:1 输出类型:CMOS，推挽式，满摆幅，TTL 电压 - 电源，单路/双路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 电压 - 输入偏移（最小值）:5mV @ 5.5V 电流 - 输入偏压（最小值）:1pA @ 5.5V 电流 - 输出（标准）:- 电流 - 静态（最大值）:24µA CMRR, PSRR（标准）:80dB CMRR，80dB PSRR 传输延迟（最大）:450ns 磁滞:±3mV 工作温度:-40°C ~ 85°C 封装/外壳:6-WFBGA，CSPBGA 安装类型:表面贴装 包装:管件 其它名称:Q3554586 |
| LT1720IS8#PBF | 功能描述:IC COMP R-RINOUT DUAL 8-SOIC RoHS:是 类别:集成电路 (IC) >> 线性 - 比较器 系列:UltraFast™ 标准包装:1 系列:- 类型:通用 元件数:1 输出类型:CMOS，开路集电极，TTL 电压 - 电源，单路/双路(±):2.7 V ~ 5.5 V 电压 - 输入偏移（最小值）:7mV @ 5V 电流 - 输入偏压（最小值）:0.25µA @ 5V 电流 - 输出（标准）:84mA @ 5V 电流 - 静态（最大值）:120µA CMRR, PSRR（标准）:- 传输延迟（最大）:600ns 磁滞:- 工作温度:-40°C ~ 85°C 封装/外壳:SC-74A，SOT-753 安装类型:表面贴装 包装:剪切带 (CT) 产品目录页面:1268 (CN2011-ZH PDF) 其它名称:*LMV331M5*LMV331M5/NOPBLMV331M5CT |
| LT1720IS8#PBF | 制造商:Linear Technology 功能描述:ICVOLT COMPARATORDUALBIPOLA 制造商:Linear Technology 功能描述:IC,VOLT COMPARATOR,DUAL,BIPOLAR,SOP,8PIN |
| LT1720IS8#TR | 功能描述:IC COMP DUAL R-R 4MA 4.5NS 8SOIC RoHS:否 类别:集成电路 (IC) >> 线性 - 比较器 系列:UltraFast™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:通用 元件数:1 输出类型:CMOS，推挽式，满摆幅，TTL 电压 - 电源，单路/双路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 电压 - 输入偏移（最小值）:5mV @ 5.5V 电流 - 输入偏压（最小值）:1pA @ 5.5V 电流 - 输出（标准）:- 电流 - 静态（最大值）:24µA CMRR, PSRR（标准）:80dB CMRR，80dB PSRR 传输延迟（最大）:450ns 磁滞:±3mV 工作温度:-40°C ~ 85°C 封装/外壳:6-WFBGA，CSPBGA 安装类型:表面贴装 包装:管件 其它名称:Q3554586 |
| LT1720IS8#TRPBF | 功能描述:IC COMP R-RINOUT DUAL 8-SOIC RoHS:否 类别:集成电路 (IC) >> 线性 - 比较器 系列:UltraFast™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:通用 元件数:1 输出类型:CMOS，推挽式，满摆幅，TTL 电压 - 电源，单路/双路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 电压 - 输入偏移（最小值）:5mV @ 5.5V 电流 - 输入偏压（最小值）:1pA @ 5.5V 电流 - 输出（标准）:- 电流 - 静态（最大值）:24µA CMRR, PSRR（标准）:80dB CMRR，80dB PSRR 传输延迟（最大）:450ns 磁滞:±3mV 工作温度:-40°C ~ 85°C 封装/外壳:6-WFBGA，CSPBGA 安装类型:表面贴装 包装:管件 其它名称:Q3554586 |
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