参数资料
型号: LT1738EG#PBF
厂商: Linear Technology
文件页数: 14/20页
文件大小: 0K
描述: IC REG CTRLR PWM CM 20-SSOP
标准包装: 66
PWM 型: 电流模式
输出数: 1
频率 - 最大: 250kHz
占空比: 93.5%
电源电压: 2.55 V ~ 20 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 20-SSOP(0.209",5.30mm 宽)
包装: 管件
产品目录页面: 1328 (CN2011-ZH PDF)
LT1738
APPLICATIO S I FOR ATIO
most of the control circuitry of the regulator. Note after the
control circuitry powers on, gate driver activity will depend
on the voltage of V IN with respect to the voltage on GCL.
As the SHDN pin enables the internal regulator a 24 μ A
current will be sourced from the pin that can provide
Frequency Compensation
Loop frequency compensation is accomplished by way of
a series RC network on the output of the error amplifier
(V C pin).
hysteresis for undervoltage lockout. This hysteresis can
be used to prevent part shutdown due to input voltage sag
from an initial high current draw.
In addition to the current hysteresis, there is also approxi-
R VC
2k
C VC
0.01 μ F
C VC2
4.7nF
V C PIN
1738 F05
mately 100mV of voltage hysteresis on the SHDN pin.
When the SHDN pin is greater than 2.2V, the hysteretic
current from the part will be reduced to essentially zero.
If a resistor divider is used to set the turn on threshold then
the resistors are determined by the following equations:
Figure 5
Referring to Figure 5, the main pole is formed by capacitor
C VC and the output impedance of the error amplifier
(approximately 400k ? ). The series resistor R VC creates a
V ON = ?
? RA + RB ?
?
?
? ? V SHDN
RB
RA
V IN
“zero” which improves loop stability and transient re-
sponse. A second capacitor C VC2 , typically one-tenth the
size of the main compensation capacitor, is sometimes
= RA ? ?
+ I SHDN ?
V HYST
? ? V SHDN
? RA RB
?
?
RB
SHDN
used to reduce the switching frequency ripple on the V C
pin. V C pin ripple is caused by output voltage ripple
attenuated by the output divider and multiplied by the error
( V HYST ? V SHDN ? V ON ? ? V SHDN )
( I SHDN ? V SHDN )
( V HYST ? V SHDN ? V ON ? ? V SHDN )
[ I SHDN ? ( V ON SHDN ) ]
V CPINRIPPLE =
Reworking these equations yields:
RA =
RB =
? V
So if we wanted to turn on at 20V with 2V of hysteresis:
amplifier. Without the second capacitor, V C pin ripple is:
1.25 ? V RIPPLE ? gm ? R VC
V OUT
where V RIPPLE = Output ripple (V P-P )
gm = Error amplifier transconductance
R VC = Series resistor on V C pin
V OUT = DC output voltage
RA =
RB =
2 V ? 1 . 39 V ? 20 V ? 0 . 1 V
24 μ A ? 1 . 39 V
2 V ? 1 . 39 V ? 20 V ? 0 . 1 V
24 μ A ? ( 20 V ? 1 . 39 V )
= 23 . 4 k
= 1 . 75 k
To prevent irregular switching, V C pin ripple should be
kept below 50mV P-P . Worst-case V C pin ripple occurs at
maximum output load current and will also be increased if
poor quality (high ESR) output capacitors are used. The
addition of a 0.0047 μ F capacitor for C VC2 pin reduces
Resistor values could be altered further by adding zeners
in the divider string. A resistor in series with SHDN pin
could further change hysteresis without changing turn on
switching frequency ripple to only a few millivolts. A low
value for R VC will also reduce V C pin ripple, but loop phase
margin may be inadequate.
voltage.
1738fa
14
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