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| 型号： | LT1738IG#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 13/20页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR PWM CM 20-SSOP |
| 标准包装： | 66 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 250kHz |
| 占空比： | 93.5% |
| 电源电压： | 2.55 V ~ 20 V |
| 降压： | 无 |
| 升压： | 是 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 是 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 20-SSOP（0.209"，5.30mm 宽） |
| 包装： | 管件 |
LT1738
APPLICATIO S I FOR ATIO
Table 2
INPUT VOLTAGE
CAPACITOR VALUE
FB PIN
R1
V OUT
< 25V
50V
100V
5pF
2.5pF
1pF
R2
Figure 3
1738 F03
Smaller value capacitors can be made in two ways. The
first is simply combining two capacitors in series. The
equivalent capacitance is then (C1 ? C2)/(C1 + C2).
The second method makes use of a capacitor divider. Care
should be taken that the voltage rating of the capacitor
satisfies the full voltage swing thus essentially the same
rating as the MOSFET.
The equivalent slew capacitance for Figure 2 is
Negative Output Voltage Setting
Negative output voltage can be sensed using the NFB pin.
In this case regulation will occur when the NFB pin is at
–2.5V. The nominal input bias current for the NFB is –25 μ A
(I NFB ), which needs to be accounted for in setting up the
divider.
Referring to Figure 4, R1 is chosen such that:
R 1 = R 2 ?
? 2 . 5 + R 2 ? 25 μ A ?
(C1 ? C2)/(C1 + C2 + C3).
MOSFET DRAIN
? V OUT ? 2 . 5 ?
?
CAP
C2
C1
A suggested value for R2 is 2.5k. The NFB pin is normally
C3
1738 F02
left open if the FB pin is being used.
Figure 2
Positive Output Voltage Setting
NFB PIN
I NFB
R2
R1
–V OUT
R 1 = R 2 ? OUT ? 1 ?
Sensingofapositiveoutputvoltageisusuallydoneusing
a resistor divider from the output to the FB pin. The
positive input to the error amp is connected internally to a
1.25V bandgap reference. The FB pin will regulate to this
voltage.
Referring to Figure 3, R1 is determined by:
? V ?
? 1 . 25 ?
The FB bias current represents a small error and can
usually be ignored for values of R1||R2 up to 10k.
One word of caution, sometimes a feedback zero is added
to the control loop by placing a capacitor across R1. If the
feedback capacitively pulls the FB pin above the internal
regulator voltage (2.4V), output regulation may be dis-
rupted. A series resistance with the feedback pin can
eliminate this potential problem. There is an internal clamp
on FB that clamps at 0.7V above the regulation voltage that
should also help prevent this problem.
1738 F04
Figure 4
Dual Polarity Output Voltage Sensing
Certain applications may benefit from sensing both posi-
tive and negative output voltages. When doing this each
output voltage resistor divider is individually set as previ-
ously described. When both FB and NFB pins are used, the
LT1738 will act to prevent either output from going
beyond its set output voltage. The highest output (lightest
load) will dominate control of the regulator. This technique
would prevent either output from going unregulated high
at no load. However, this technique will also compromise
output load regulation.
Shutdown
If SHDN is pulled low, the regulator will turn off. As the
SHDN pin voltage is increased from ground the internal
bandgap regulator will be powered on. This will set a 1.39V
threshold for turn on of the internal regulator that runs
1738fa
13
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| LT1739CFE#TR | 功能描述:IC AMP XDSL LINE DRV DUAL20TSSOP RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:27 系列:- 类型:收发器 驱动器/接收器数:3/3 规程:RS232，RS485 电源电压:4.75 V ~ 5.25 V 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC 包装:管件 |
| LT1739CFE#TRPBF | 功能描述:IC AMP XDSL LINE DRV DUAL20TSSOP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:27 系列:- 类型:收发器 驱动器/接收器数:3/3 规程:RS232，RS485 电源电压:4.75 V ~ 5.25 V 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC 包装:管件 |
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