参数资料
型号: LT1777CS#PBF
厂商: Linear Technology
文件页数: 16/24页
文件大小: 0K
描述: IC REG BUCK ADJ 0.7A 16SOIC
标准包装: 50
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.24 V ~ 30 V
输入电压: 12 V ~ 48 V
PWM 型: 电流模式
频率 - 开关: 100kHz
电流 - 输出: 700mA
同步整流器:
工作温度: 0°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
包装: 管件
供应商设备封装: 16-SOIC
LT1777
APPLICATIO N S I N FOR M ATIO N
As an example, assume that the capacitance between the
V SW node and a high impedance pin node is 0.1pF, and that
the high impedance node in question exhibits a capaci-
tance of 1pF to ground. Also assume a “typical” 36V IN to
5V OUT application. Due to the large voltage excursion at
the V SW node, this will couple a 3.5V(!) transient to the
high impedance pin, causing abnormal operation. An
explicit 100pF capacitor added to the node will reduce the
amplitude of the disturbance to more like 35mV (although
settling time will increase).
Specific pin recommendations are as follows:
SHDN: If unused, add a 100pF capacitor to ground.
SYNC: Ground if unused.
V C : Add a capacitor directly to ground in addition to the
explicit compensation network. A value of one-tenth of
the main compensation capacitor is recommended, up
to a maximum of 100pF.
FB: Assuming the V C pin is handled properly, this pin
usually requires no explicit capacitor of its own, but
keep this node physically small to minimize stray
capacitance.
16
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