参数资料
| 型号： | LT1786FCS#TR |
| 厂商： | Linear Technology |
| 文件页数： | 13/20页 |
| 文件大小： | 0K |
| 描述： | IC REG SW CCFL SMBUS PROG 16SOIC |
| 标准包装： | 2,500 |
| 应用： | 转换器，CCFL |
| 输入电压： | 4.5 V ~ 30 V |
| 输出数： | 1 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
LT1786F
APPLICATIO N S I N FOR M ATIO N
value (see Block Diagram). A STOP condition is optional.
The command code and data byte are defined with the
following format:
6-Bit Current Output DAC
The 6-bit current output DAC is guaranteed monotonic and
is digitally adjustable in 63 equal steps. On power-up, if
Command Code
Data Byte
ADR connects to V CC , the 6-bit internal register C (see
7
6 5 4 3 2 1 0
7
6
5
4
3
2
1
0
Block Diagram) resets to 100000B and the DAC output is
SHDN X X X X X X X
D5 D4 D3 D2 D1 D0 X
X
set to midrange. On power-up, if ADR connects to ground,
SHDN: 0 for normal operation, 1 for shutdown
D5 to D0: DAC Data Byte Bits, D5 is the Most Significant Bit
START and STOP Conditions
At the beginning of any SMBus communication, the mas-
ter must transmit a START condition by switching SDA
from high to low while SCL is high. When a master has
finished communicating with a slave device, a STOP
condition is issued by switching SDA from low to high
while SCL is high. The SMBus is then free for communi-
cation with another SMBus device.
Early STOP Conditions
The LT1786F recongnizes a STOP condition at any point in
the SMBus communication sequence. If the STOP occurs
prematurely before the data byte is acknowledged in the
Write Byte protocol, the DAC output current value is not
updated; otherwise internal register C is updated with the
new data and the DAC output current changes
correspondingly.
The Slave Address
The LT1786F responds to one of two 7-bit addresses. The
first five bits have been factory programmed to 01011. The
last two address bits are programmed by the user by tying
the ADR pin to V CC or GND (see functional table)
register C resets to 000000B and the DAC output is set to
zero. For the LT1786F, the current source output (I OUT )
can be biased from – 10V to (V CC – 1.3V). Full-scale
current is trimmed to ± 2% at room temperature and ± 4%
over the commercial temperature range.
Shutdown
Three methods may be employed to shut down the LT1786F
(see Block Diagram).
The LT1786F enters SMBus suspend mode if a logic low
level is applied to the SMBSUS pin or a logic high level is
applied to Bit 7 in the Command Byte of the SMBus
communication sequence. In SMBus suspend mode, sup-
ply current typically drops to 40 μ A and the last output
current setting is internally retained. The DAC resumes
this level upon its return to normal operation. Enabling an
SMBus suspend condition also turns on an open-drain
N-channel MOSFET which pulls the SHDN pin low. The
N-channel device sinks up to 1.6mA at the SHDN pin and
its logic low level is guaranteed to less than 0.4V.
The LT1786F enters regulator shutdown mode if a logic
low level is applied to the SHDN pin. In this mode, supply
current typically drops to 150 μ A, the switching regulator
circuitry is shut down and the DAC is kept alive. The DAC
output current setting is maintained. This feature can be
used to program the DAC to a desired output current level
ADR
GND
V CC
SMBus ADDRESS
0101101
0101100
DAC POWER-UP VALUE
Zero Scale
Midscale
(other than the preset zero-scale or midscale level defined
by the selected SMBus address) before allowing the CCFL
regulator to turn on.
13
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