参数资料
型号: LT1912EDD#PBF
厂商: Linear Technology
文件页数: 16/24页
文件大小: 0K
描述: IC REG BUCK ADJ 2A 10DFN
标准包装: 121
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.79 V ~ 20 V
输入电压: 3.6 V ~ 36 V
PWM 型: 电流模式
频率 - 开关: 200kHz ~ 500kHz
电流 - 输出: 2A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 10-WFDFN 裸露焊盘
包装: 管件
供应商设备封装: 10-DFN(3x3)
产品目录页面: 1329 (CN2011-ZH PDF)
LT1912
APPLICATIONS INFORMATION
The SW and BOOST nodes should be as small as possible.
Finally, keep the FB and V C nodes small so that the ground
traces will shield them from the SW and BOOST nodes.
The exposed pad on the bottom of the package must be
soldered to ground so that the pad acts as a heat sink. To
keep thermal resistance low, extend the ground plane as
much as possible, and add thermal vias under and near
the LT1912 to additional ground planes within the circuit
board and on the bottom side.
L1
V OUT
C2
R RT
C C
R C
VIAS TO V OUT
VIAS TO SYNC
HotPluggingSafely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of LT1912 circuits. However, these capaci-
tors can cause problems if the LT1912 is plugged into a
live supply (see Linear Technology Application Note 88 for
a complete discussion). The low loss ceramic capacitor,
combined with stray inductance in series with the power
source, forms an under damped tank circuit, and the
voltage at the V IN pin of the LT1912 can ring to twice the
nominal input voltage, possibly exceeding the LT1912’s
rating and damaging the part. If the input supply is poorly
controlled or the user will be plugging the LT1912 into an
energized supply, the input network should be designed
to prevent this overshoot. Figure 9 shows the waveforms
that result when an LT1912 circuit is connected to a 24V
supply through six feet of 24-gauge twisted pair. The
first plot is the response with a 4.7μF ceramic capacitor
at the input. The input voltage rings as high as 50V and
the input current peaks at 26A. A good solution is shown
in Figure 9b. A 0.7Ω resistor is added in series with the
input to eliminate the voltage overshoot (it also reduces
the peak input current). A 0.1μF capacitor improves high
frequency filtering. For high input voltages its impact on
efficiency is minor, reducing efficiency by 1.5 percent for
a 5V output at full load operating from 24V.
R2
R1
D1 C1
GND
1912 F08
VIAS TO LOCAL GROUND PLANE VIAS TO RUN/SS VIAS TO V IN
OUTLINE OF LOCAL
GROUND PLANE
Figure 8. A Good PCB Layout Ensures Proper, Low EMI Operation
High Temperature Considerations
The PCB must provide heat sinking to keep the LT1912
cool. The exposed pad on the bottom of the package must
be soldered to a ground plane. This ground should be tied
to large copper layers below with thermal vias; these lay-
ers will spread the heat dissipated by the LT1912. Place
additional vias can reduce thermal resistance further. With
these steps, the thermal resistance from die (or junction)
to ambient can be reduced to JA = 35°C/W or less. With
100 LFPM airflow, this resistance can fall by another 25%.
Further increases in airflow will lead to lower thermal re-
sistance. Because of the large output current capability of
the LT1912, it is possible to dissipate enough heat to raise
the junction temperature beyond the absolute maximum of
1912fa
16
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