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参数资料
| 型号： | LT1913IDD#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 17/24页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 3.5A 10DFN |
| 标准包装： | 121 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.79 V ~ 25 V |
| 输入电压： | 3.6 V ~ 25 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 200kHz ~ 2.4MHz |
| 电流 - 输出： | 3.5A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-WFDFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 10-DFN（3x3） |
LT1913
APPLICATIONS INFORMATION
the output is held high, then parasitic diodes inside the
LT1913 can pull large currents from the output through
the SW pin and the V IN pin. Figure 7 shows a circuit that
will run only when the input voltage is present and that
protects against a shorted or reversed input.
The Exposed Pad on the bottom of the package must be
soldered to ground so that the pad acts as a heat sink. To
keep thermal resistance low, extend the ground plane as
much as possible, and add thermal vias under and near
the LT1913 to additional ground planes within the circuit
board and on the bottom side.
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board layout. Figure 8 shows
the recommended component placement with trace,
ground plane and via locations. Note that large, switched
currents ?ow in the LT1913’s V IN and SW pins, the catch
diode (D1) and the input capacitor (C1). The loop formed
by these components should be as small as possible. These
components, along with the inductor and output capacitor,
should be placed on the same side of the circuit board,
and their connections should be made on that layer. Place
a local, unbroken ground plane below these components.
The SW and BOOST nodes should be as small as possible.
Finally, keep the FB and V C nodes small so that the ground
traces will shield them from the SW and BOOST nodes.
D4
MBRS140
Hot Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of LT1913 circuits. However, these capaci-
tors can cause problems if the LT1913 is plugged into a
live supply (see Linear Technology Application Note 88 for
a complete discussion). The low loss ceramic capacitor,
combined with stray inductance in series with the power
source, forms an under damped tank circuit, and the
voltage at the V IN pin of the LT1913 can ring to twice the
nominal input voltage, possibly exceeding the LT1913’s
rating and damaging the part. If the input supply is poorly
controlled or the user will be plugging the LT1913 into an
energized supply, the input network should be designed
V IN
V IN
BOOST
L1
V OUT
C2
LT1913
RUN/SS
V C
SW
V OUT
R RT
C C
GND FB
BACKUP
R C
R2
1913 F07
R1
Figure 7. Diode D4 Prevents a Shorted Input from
D1
C1
Discharging a Backup Battery Tied to the Output. It Also
Protects the Circuit from a Reversed Input. The LT1913
GND
R PG
Runs Only When the Input is Present
1913 F08
VIAS TO LOCAL GROUND PLANE
VIAS TO RUN/SS
VIAS TO V IN
VIAS TO V OUT
VIAS TO SYNC
VIAS TO PG
OUTLINE OF LOCAL
GROUND PLANE
Figure 8. A Good PCB Layout Ensures Proper, Low EMI Operation
1913f
17
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