参数资料
型号: LT1962EMS8-5#PBF
厂商: Linear Technology
文件页数: 15/16页
文件大小: 0K
描述: IC REG LDO 5V .3A 8-MSOP
产品培训模块: More Information on LDOs
标准包装: 50
稳压器拓扑结构: 正,固定式
输出电压: 5V
输入电压: 最高 20V
电压 - 压降(标准): 0.27V @ 300mA
稳压器数量: 1
电流 - 输出: 300mA
电流 - 限制(最小): 320mA
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-MSOP
包装: 管件
产品目录页面: 1329 (CN2011-ZH PDF)
配用: DC1075A-ND - BOARD COMPANION
LT1962 Series
APPLICATIO S I FOR ATIO
from the 1.22V reference when the output is forced to 20V.
The top resistor of the resistor divider must be chosen to
limit the current into the ADJ pin to less than 5mA when the
ADJ pin is at 7V. The 13V difference between OUT and ADJ
or a second regulator circuit. The state of the SHDN pin will
have no effect on the reverse output current when the
output is pulled above the input.
pin divided by the 5mA maximum current into the ADJ pin
yields a minimum top resistor value of 2.6k.
In circuits where a backup battery is required, several
100
T J = 25 ° C
90 V IN = 0V
CURRENT FLOWS
80 INTO OUTPUT PIN
70 V OUT = V ADJ (LT1962)
LT196 2
different input/output conditions can occur. The output
voltage may be held up while the input is either pulled to
ground, pulled to some intermediate voltage or is left open
circuit. Current flow back into the output will follow the
curve shown in Figure 7.
60
50
40
30
20
LT1962-1.5
LT1962-1.8
LT1962-2.5
LT1962-3
LT1962-3.3
When the IN pin of the LT1962 is forced below the OUT pin
or the OUT pin is pulled above the IN pin, input current will
typically drop to less than 2 μ A. This can happen if the input
of the device is connected to a discharged (low voltage)
10
0
0
1
2
LT1962-5
3 4 5 6 7 8
OUTPUT VOLTAGE (V)
9 10
1962 F07
battery and the output is held up by either a backup battery
Figure 7. Reverse Output Current
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.007
(0.18)
0 ° – 6 ° TYP
0.118 ± 0.004 *
(3.00 ± 0.102)
0.193 ± 0.006
(4.90 ± 0.15)
0.043
(1.10)
MAX
8
1
7 6
2 3
5
4
0.118 ± 0.004**
(3.00 ± 0.102)
0.034
(0.86)
REF
SEATING
0.021 ± 0.006
(0.53 ± 0.015)
PLANE
0.009 – 0.015
(0.22 – 0.38)
0.0256
(0.65)
0.005 ± 0.002
(0.13 ± 0.05)
MSOP (MS8) 1100
BSC
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
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