参数资料
型号: LT1970CFE#PBF
厂商: Linear Technology
文件页数: 5/26页
文件大小: 0K
描述: IC OPAMP ADJ CURR LIMIT 20-TSSOP
标准包装: 74
放大器类型: 通用
电路数: 1
转换速率: 1.6 V/µs
增益带宽积: 3.6MHz
电流 - 输入偏压: 160nA
电压 - 输入偏移: 200µV
电流 - 电源: 7mA
电流 - 输出 / 通道: 800mA
电压 - 电源,单路/双路(±): 5 V ~ 36 V,±2.5 V ~ 18 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)裸露焊盘
供应商设备封装: 20-TSSOP-EP
包装: 管件
产品目录页面: 1320 (CN2011-ZH PDF)
LT1970
13
1970fc
APPLICATIONS INFORMATION
take protective measures when a current limit condition
is detected automatically.
The current limit status ag can also be used to produce
a dramatic change in the current limit value of the ampli-
er. Figure 4 illustrates a “snap-back” current limiting
characteristic. In this circuit, a simple resistor network
initially sets a high value of current limit (500mA). The
circuit operates normally until the signal is large enough
to enter current limit. When either current limit ag goes
low, the current limit control voltage is reduced by a fac-
tor of 10. This then forces a low level of output current
(50mA) until the signal is reduced in magnitude. When
the load current drops below the lower level, the current
limit is then restored to the higher value. This action is
similar to a self resettable fuse that trips at dangerously
high current levels and resets only when conditions are
safe to do so.
THERMAL MANAGEMENT
Minimizing Power Dissipation
The LT1970 can operate with up to 36V total supply volt-
age with output currents up to ± 500mA. The amount of
power dissipated in the chip could approach 18W under
worst-case conditions. This amount of power will cause
die temperature to rise until the circuit enters thermal
shutdown. While the thermal shutdown feature prevents
damage to the circuit, normal operation is impaired.
Thermal design of the LT1970 operating environment is
essential to getting maximum utility from the circuit.
The rst concern for thermal management is minimizing
the heat which must be dissipated. The separate power
pins V+ and Vcan be a great aid in minimizing on-chip
power. The output pin can swing to within 1.0V of V+ or
Veven under maximum output current conditions. Using
separate power supplies, or voltage regulators, to set V+
Figure 3. Adding Positive Feedback to Sharpen the Transition
Edges of the Current Limit Status Flags
Figure 4. “Snap-Back” Current Limiting
VCSRC
COMMON
VEE
VCSNK
V
FILTER
V+
12V
ISOURCE FLAG
WHEN CURRENT LIMIT
IS FLAGGED, ILIMIT
TRESHOLD IS REDUCED
BY 0.5%
ISINK FLAG
EN
VCC
ISNK
ISRC
SENSE
SENSE+
TSD
OUT
+IN
VIN
LT1970
–12V
–IN
RS
RL
1970 F03
RG
RF
R2
100Ω
R1
100Ω
CURRENT
LIMIT
CONTROL
VOLTAGE
(0.1V TO 5V)
R4
20k
R3
20k
VCSRC
COMMON
VEE
VCSNK
V
FILTER
V+
12V
EN
VCC
ISNK
ISRC
SENSE
SENSE+
TSD
OUT
+IN
VIN
LT1970
–12V
–IN
RS
RL
1970 F04
RG
10k
RF
10k
R3
2.55k
R2
39.2k
R1
54.9k
IMAX
500mA
–500mA
50mA
0
IOUT
ILOW
VCC R2
(R1 + R2) 10 RS
IMAX
VCC (R2||R3)
[R1 + (R2||R3)] 10 RS
ILOW
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