参数资料
| 型号： | LT3013MPFE#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 14/20页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO ADJ .25A 16-TSSOP |
| 产品培训模块： | More Information on LDOs |
| 标准包装： | 95 |
| 稳压器拓扑结构： | 正，可调式 |
| 输出电压： | 1.24 V ~ 60 V |
| 输入电压： | 4 V ~ 80 V |
| 电压 - 压降（标准）： | 0.4V @ 250mA |
| 稳压器数量： | 1 |
| 电流 - 输出： | 250mA |
| 电流 - 限制（最小）： | 250mA |
| 工作温度： | -55°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 供应商设备封装： | 16-TSSOP-EP |
| 包装： | 管件 |
LT3013
APPLICATIONS INFORMATION
Figure 4 shows a block diagram of the PWRGD circuit. At
startup, the timing capacitor is discharged and the PWRGD
pin will be held low. As the output voltage increases and
the ADJ pin crosses the 90% threshold, the JK ?ip-?op
is reset, and the 3μA current source begins to charge the
timing capacitor. Once the voltage on the C T pin reaches
the V CT(HIGH) threshold (approximately 1.7V at 25°C), the
capacitor voltage is clamped and the PWRGD pin is set to
a high impedance state.
During normal operation, an internal glitch ?lter will ignore
short transients (<15μs). Longer transients below the 90%
threshold will reset the JK ?ip-?op. This ?ip-?op ensures
that the capacitor on the C T pin is quickly discharged all
the way to the V CT(LOW) threshold before re-starting the
time delay. This provides a consistent time delay after the
ADJ pin is within 10% of the regulated voltage before the
PWRGD pin switches to high impedance.
Thermal Considerations
The power handling capability of the device will be limited
by the maximum rated junction temperature (125°C
for LT3013E, LT3013MP or 140°C for LT3013HFE). The
power dissipated by the device will be made up of two
components:
1. Output current multiplied by the input/output voltage
differential: I OUT ? (V IN – V OUT ) and,
2. GND pin current multiplied by the input voltage:
I GND ? V IN .
The GND pin current can be found by examining the GND Pin
Current curves in the Typical Performance Characteristics.
Power dissipation will be equal to the sum of the two
components listed above.
The LT3013 has internal thermal limiting designed
to protect the device during overload conditions. For
continuous normal conditions the maximum junction
temperature rating of 125°C (E-grade, MP-grade) or 140°C
(H-grade)must not be exceeded. It is important to give
careful consideration to all sources of thermal resistance
from junction to ambient. Additional heat sources mounted
nearby must also be considered.
I CT 3μA
C T
PWRGD
ADJ
+
J
Q
V CT(HIGH) – V BE
(~1.1V)
V REF ? 90%
–
K
V CT(LOW)
~0.1V
3013 F04
Figure 4. PWRGD Circuit Block Diagram
3013fe
14
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