参数资料
| 型号： | LT3071IUFD#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 11/28页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO ADJ 5A 28QFN |
| 标准包装： | 73 |
| 稳压器拓扑结构： | 正，可调式 |
| 输出电压： | 0.8 V ~ 1.8 V |
| 输入电压： | 0.95 V ~ 3 V |
| 电压 - 压降（标准）： | 0.085V @ 5A |
| 稳压器数量： | 1 |
| 电流 - 输出： | 5A |
| 电流 - 限制（最小）： | 5.1A |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-QFN（4x5） |
| 包装： | 管件 |
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LT3071
PIN FUNCTIONS
VIOC (Pin 1): Voltage for In-to-Out Control. The IC incorpo-
rates a unique tracking function to control a buck regulator
powering the LT3071’s input. The VIOC pin is the output
of this tracking function that drives the buck regulator to
maintain the LT3071’s input voltage at V OUT + 300mV.
This function maximizes efficiency and minimizes power
dissipation. See the Applications Information section for
more information on proper control of the buck regulator.
PWRGD (Pin 2): Power Good. The PWRGD pin is an open-
drain NMOS output that actively pulls low if any one of
these fault modes is detected:
? V OUT is less than 90% of V OUT(NOMINAL) on the rising
edge of V OUT .
? V OUT drops below 85% of V OUT(NOMINAL) for more than
25μs.
? Junction temperature typically exceeds 145°C.
? V BIAS is less than its undervoltage lockout threshold.
? The OUT-to-IN reverse-current detector activates.
See the Applications Information section for more infor-
mation on PWRGD fault modes.
REF/BYP (Pin 3): Reference Filter. The pin is the output
of the bandgap reference and has an impedance of ap-
proximately 19kΩ. This pin must not be externally loaded.
Bypassing the REF/BYP pin to GND with a 10nF capacitor
decreases output voltage noise and provides a soft-start
function to the reference. LTC recommends the use of a
high quality, low leakage capacitor. See the Applications
Information section for more information on noise and
output voltage margining considerations.
GND (Pins 4, 9-14, 20, 26, Exposed Pad Pin 29): Ground.
The exposed pad of the QFN package is an electrical con-
nection to GND. To ensure proper electrical and thermal
performance, solder Pin 29 to the PCB ground and tie to
all GND pins of the package. These GND pins are fused
to the internal die attach paddle and the exposed pad to
optimize heat sinking and thermal resistance characteris-
tics. See the Applications Information section for thermal
considerations and calculating junction temperature.
IN (Pins 5, 6, 7, 8): Input Supply. These pins supply
power to the high current pass transistor. Tie all IN pins
together for proper performance. The LT3071 requires a
bypass capacitor at IN to maintain stability and low input
impedance over frequency. A 47μF input bypass capacitor
suffices for most battery and power plane impedances.
Minimizing input trace inductance optimizes performance.
Applications that operate with low V IN -V OUT differential
voltages and that have large, fast load transients may require
much higher input capacitor requirements to prevent the
input supply from drooping and allowing the regulator to
enter dropout. See the Applications Information section
for more information on input capacitor requirements.
OUT (Pins 15, 16, 17, 18): Output. These pins supply
power to the load. Tie all OUT pins together for proper
performance. A minimum output capacitance of 15μF is
required for stability. LTC recommends low ESR, X5R or
X7R dielectric ceramic capacitors for best performance.
A parallel ceramic capacitor combination of 10μF + 4.7μF
+ 2.2μF or 15 1μF ceramic capacitors in parallel provide
excellent stability and load transient response. Large load
transient applications require larger output capacitors to
limit peak voltage transients. See the Applications Infor-
mation section for more information on output capacitor
requirements.
SENSE (Pin 19): Kelvin Sense for OUT . The SENSE pin is
the inverting input to the error amplifier. Optimum regu-
lation is obtained when the SENSE pin is connected to
the OUT pins of the regulator. In critical applications, the
resistance (R P ) of PCB traces between the regulator and the
load cause small voltage drops, creating a load regulation
error at the point of load. Connecting the SENSE pin at
the load instead of directly to OUT eliminates this voltage
error. Figure 1 illustrates this Kelvin-Sense connection
method. Note that the voltage drop across the external
PCB traces adds to the dropout voltage of the regulator.
The SENSE pin input bias current depends on the selected
output voltage. SENSE pin input current varies from 50μA
typically at V OUT = 0.8V to 300μA typically at V OUT = 1.8V.
3071fb
For more information www.linear.com/3071
11
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LT3071IUFD-TR | 制造商:LINER 制造商全称:Linear Technology 功能描述:5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator with Analog Margining |
| LT3071IUFD-TRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator with Analog Margining |
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| LT3071MPUFD#PBF | 功能描述:IC REG LDO ADJ 5A 28QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 标准包装:3,000 系列:- 稳压器拓扑结构:正，固定式 输出电压:3V 输入电压:最高 5.5V 电压 - 压降（标准）:0.12V @ 150mA 稳压器数量:1 电流 - 输出:150mA（最小值） 电流 - 限制（最小）:220mA 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:SOT-23-5 细型，TSOT-23-5 供应商设备封装:TSOT-23-5 包装:带卷 (TR) 其它名称:ADP160AUJZ-3.0-R7TR |
| LT3071MPUFD#PBF | 制造商:Linear Technology 功能描述:IC ADJ LDO REG 0.8V TO 1.8V 5A QFN28 |
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