参数资料
型号: LT3412AEFE
厂商: LINEAR TECHNOLOGY CORP
元件分类: 稳压器
英文描述: 3 A SWITCHING REGULATOR, 4 kHz SWITCHING FREQ-MAX, PDSO16
封装: 4.4 MM, PLASTIC, TSSOP-16
文件页数: 4/20页
文件大小: 267K
代理商: LT3412AEFE
LTC3412A
12
3412afb
Output Voltage Programming
The output voltage is set by an external resistive divider
according to the following equation:
VV
R
OUT
=+
08
1
2
1
.
The resistive divider allows pin VFB to sense a fraction of
the output voltage as shown in Figure 2.
IBURST is determined by the desired amount of output
voltage ripple. As the value of IBURST increases, the sleep
period between pulses and the output voltage ripple in-
crease. The burst clamp voltage, VBURST, can be set by a
resistor divider from the VFB pin to the SGND pin as shown
in Figure 1.
Pulse skipping, which is a compromise between low
output voltage ripple and efficiency, can be implemented
by connecting pin SYNC/MODEto ground. This sets IBURST
to 0A. In this condition, the peak inductor current is limited
by the minimum on-time of the current comparator. The
lowest output voltage ripple is achieved while still operat-
ing discontinuously. During very light output loads, pulse
skipping allows only a few switching cycles to be skipped
while maintaining the output voltage in regulation.
Frequency Synchronization
The LTC3412A’s internal oscillator can be synchronized to
an external clock signal. During synchronization, the top
MOSFET turn-on is locked to the falling edge of the
external frequency source. The synchronization frequency
range is 300kHz to 4MHz. Synchronization only occurs if
the external frequency is greater than the frequency set
by the external resistor. Because slope compensation is
generated by the oscillator’s RC circuit, the external
frequency should be set 25% higher than the frequency
set by the external resistor to ensure that adequate slope
compensation is present.
Soft-Start
The RUN/SS pin provides a means to shut down the
LTC3412A as well as a timer for soft-start. Pulling the
RUN/SS pin below 0.5V places the LTC3412A in a low
quiescent current shutdown state (IQ < 1μA).
The LTC3412A contains an internal soft-start clamp that
gradually raises the clamp on ITH after the RUN/SS pin is
pulled above 2V. The full current range becomes available
on ITH after 1024 switching cycles. If a longer soft-start
period is desired, the clamp on ITH can be set externally
with a resistor and capacitor on the RUN/SS pin as shown
in Figure 1. The soft-start duration can be calculated by
using the following formula:
tR
C
V
VV
SECONDS
SS
IN
=
ln
–.
()
18
APPLICATIO S I FOR ATIO
WU
UU
3412A F02
LTC3412A
VFB
SGND
VOUT
R2
R1
Figure 2. Setting the Output Voltage
Burst Clamp Programming
If the voltage on the SYNC/MODE pin is less than VIN by 1V,
Burst Mode operation is enabled. During Burst Mode
Operation, the voltage on the SYNC/MODE pin determines
the burst clamp level, which sets the minimum peak
inductor current, IBURST. To select the burst clamp level,
use the graph of Minimum Peak Inductor Current vs Burst
Clamp Voltage in the Typical Performance Characteristics
section.
VBURST is the voltage on the SYNC/MODE pin. IBURST can
only be programmed in the range of 0A to 6A. For values
of VBURST greater than 1V, IBURST is set at 6A. For values
of VBURST less than 0.4V, IBURST is set at 0A. As the output
load current drops, the peak inductor currents decrease to
keep the output voltage in regulation. When the output
load current demands a peak inductor current that is less
than IBURST, the burst clamp will force the peak inductor
current to remain equal to IBURST regardless of further
reductions in the load current. Since the average inductor
current is greater than the output load current, the voltage
on the ITH pin will decrease. When the ITH voltage drops
to 150mV, sleep mode is enabled in which both power
MOSFETs are shut off along with most of the circuitry to
minimize power consumption. All circuitry is turned back
on and the power MOSFETs begin switching again when
the output voltage drops out of regulation. The value for
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