参数资料
型号: LT3434EFE#TR
厂商: Linear Technology
文件页数: 3/24页
文件大小: 0K
描述: IC REG BUCK ADJ 3A 16TSSOP
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.25 V ~ 54 V
输入电压: 3.3 V ~ 60 V
PWM 型: 电流模式,混合
频率 - 开关: 200kHz
电流 - 输出: 3A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 16-TSSOP-EP
LT3434
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T J = 25 ° C. V IN = 12V, SHDN = 12V, BIAS = 5V, FB/PGFB = 1.25V,
C SS /SYNC = 0V unless otherwise noted.
SYMBOL
I PK
PARAMETER
V C High Clamp
SW Current Limit
Switch On Resistance (Note 9)
Switching Frequency
CONDITIONS
FB = 1.15V
MIN
2.1
3
180
TYP
2.2
4.7
0.1
200
MAX
2.4
6.5
0.25
230
UNITS
V
A
?
kHz
Maximum Duty Cycle
90
92
%
Minimum SYNC Amplitude
1.5
2.0
V
SYNC Frequency Range
SYNC Input Impedance
230
500
45
kHz
k ?
I CSS
I PGFB
V PGFB
I CT
C SS Current Threshold (Note 10)
PGFB Input Current
PGFB Voltage Threshold (Note 11)
C T Source Current (Note 11)
FB = 0V
7
88
2
13
25
90
3.6
20
100
92
5.5
μ A
nA
%
μ A
C T Sink Current (Note 11)
1
2
mA
V CT
C T Voltage Threshold (Note 11)
PG Leakage (Note 11)
PG Sink Current (Note 11)
PGFB = 1V, PG = 400mV
1.16
120
1.2
0.1
200
1.26
1
V
μ A
μ A
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3434EFE is guaranteed to meet performance specifications
from 0 ° C to 125 ° C junction temperature. Specifications over the –40 ° C to
125 ° C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3434IFE is guaranteed and tested over the full –40 ° C to 125 ° C
operating junction temperature range.
Note 3: Minimum input voltage is defined as the voltage where switching
starts. Actual minimum input voltage to maintain a regulated output will
depend upon output voltage and load current. See Applications
Information.
Note 4: Supply input current is the quiescent current drawn by the input
pin. Its typical value depends on the voltage on the BIAS pin and operating
state of the LT3434. With the BIAS pin at 0V, all of the quiescent current
required to operate the LT3434 will be provided by the V IN pin. With the
BIAS voltage above its minimum input voltage, a portion of the total
quiescent current will be supplied by the BIAS pin. Supply sleep current is
defined as the quiescent current during the “sleep” portion of Burst Mode
Note 5: Minimum BIAS voltage is the voltage on the BIAS pin when I BIAS is
sourced into the pin.
Note 6: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
Note 7: Boost current is the current flowing into the BOOST pin with the
pin held 3.3V above input voltage. It flows only during switch on time.
Note 8: Gain is measured with a V C swing from 1.15V to 750mV.
Note 9: Switch on resistance is calculated by dividing V IN to SW voltage by
the forced current (3A). See Typical Performance Characteristics for the
graph of switch voltage at other currents.
Note 10: The C SS threshold is defined as the value of current sourced into
the C SS pin which results in an increase in sink current from the V C pin.
See the Soft-Start section in Applications Information.
Note 11: The PGFB threshold is defined as the percentage of V REF voltage
which causes the current source output of the C T pin to change from
sinking (below threshold) to sourcing current (above threshold). When
sourcing current, the voltage on the C T pin rises until it is clamped
internally. When the clamp is activated, the output of the PG pin will be set
to a high impedance state. When the C T clamp is inactive the PG pin will
be set active low with a current sink capability of 200 μ A.
operation. See Applications Information for determining application supply
currents.
3434fb
3
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