参数资料
型号: LT3435IFE#PBF
厂商: Linear Technology
文件页数: 15/24页
文件大小: 0K
描述: IC REG BUCK ADJ 3A 16TSSOP
标准包装: 95
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.25 V ~ 54 V
输入电压: 3.3 V ~ 60 V
PWM 型: 电流模式,混合
频率 - 开关: 500kHz
电流 - 输出: 3A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 管件
供应商设备封装: 16-TSSOP-EP
LT3435
APPLICATIO S I FOR ATIO
ramp rate. When the current through the C SS capacitor
exceeds the C SS threshold (I CSS ), the voltage ramp of the
output capacitor is limited by reducing the V C pin voltage.
The minimum average input current depends on the V IN to
V OUT ratio, V C frequency compensation, feedback divider
network and Schottky diode leakage. It can be approxi-
? V ? ( I BIASS + I FB + I S
()
I IN ( AVG ) ? I VINS + I SHDN + ? OUT ?
The C SS threshold is proportional to the FB voltage (see
Typical Performance Characteristics) and is defeated for
FB voltages greater than 0.9V (typical). The output dV/dt
can be approximated by:
mated by the following equation:
? V IN ? η
)
= CSS
dV
dt
I
C SS
where
I VINS = input pin current in sleep mode
but actual values will vary due to start-up load conditions,
compensation values and output capacitor selection.
C CSS = 1000pF
V OUT = output voltage
V IN = input voltage
I BIASS = BIAS pin current in sleep mode
I FB = feedback network current
I IN ( AVG ) = 45 μ A + 5 μ A + ?
? 12 ?
?
V OUT
1V/DIV
C CSS = 0.01μF
C CSS = 0.1μF
I S = catch diode reverse leakage at V OUT
η = low current efficiency (non Burst Mode operation)
Example: For V OUT = 3.3V, V IN = 12V
? 3 . 3 ? ( 125 μ A + 12 . 5 μ A + 0 . 5 μ A )
( 0 . 8 )
V IN = 12V
V OUT = 3.3V
1ms/DIV
3435 F04
= 45 μ A + 5 μ A + 44 μ A = 99 μ A
I L = 500mA
Figure 4. V OUT dV/dt
Burst Mode OPERATION
To enhance efficiency at light loads, the LT3435 automati-
cally switches to Burst Mode operation which keeps the
output capacitor charged to the proper voltage while
minimizing the input quiescent current. During Burst
Mode operation, the LT3435 delivers short bursts of
current to the output capacitor followed by sleep periods
150
125
100
75
50
25
0
V OUT = 3.3V
T A = 25 ° C
where the output power is delivered to the load by the
output capacitor. In addition, V IN and BIAS quiescent
currents are reduced to typically 45 μ A and 125 μ A respec-
tively during the sleep time. As the load current decreases
0
10
20 30 40
INPUT VOLTAGE (V)
Figure 5. I Q vs V IN
50
60
3435 F05
towards a no load condition, the percentage of time that
the LT3435 operates in sleep mode increases and the
average input current is greatly reduced resulting in higher
efficiency.
During the sleep portion of the Burst Mode Cycle, the V C
pin voltage is held just below the level need for normal
operation to improve transient response. See the Typical
Performance Characteristics section for burst and tran-
sient response waveforms.
3435fa
15
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