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| 型号： | LT3436EFE#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/16页 |
| 文件大小： | 0K |
| 描述： | IC REG BOOST ADJ 3A 16TSSOP |
| 标准包装： | 95 |
| 类型： | 升压（升压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1.2 V ~ 34 V |
| 输入电压： | 3 V ~ 25 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 800kHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 16-TSSOP-EP |
LT3436
APPLICATIO N S I N FOR M ATIO N
SYNCHRONIZATION
The SYNC pin, is used to synchronize the internal oscilla-
tor to an external signal. The SYNC input must pass from
a logic level low, through the maximum synchronization
threshold with a duty cycle between 20% and 80%. The
input can be driven directly from a logic level output. The
synchronizing range is equal to initial operating frequency
up to 1.4MHz. This means that minimum practical sync
frequency is equal to the worst-case high self-oscillating
frequency (960kHz), not the typical operating frequency of
800kHz. Caution should be used when synchronizing
above 1.1MHz because at higher sync frequencies the
amplitude of the internal slope compensation used to
prevent subharmonic switching is reduced. Higher induc-
tor values will tend to eliminate this problem. See Fre-
quency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insufficient slope compensa-
tion. Application Note 19 has more details on the theory
of slope compensation.
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken to achieve optimal electrical,
thermal and noise performance. For maximum efficiency,
switch rise and fall times are typically in the nanosecond
range. To prevent noise both radiated and conducted, the
L1
C3
high speed switching current path, shown in Figure 5,
must be kept as short as possible. This is implemented in
the suggested layout of Figure 6. Shortening this path will
also reduce the parasitic trace inductance of approxi-
mately 25nH/inch. At switch off, this parasitic inductance
produces a flyback spike across the LT3436 switch. When
operating at higher currents and output voltages, with
poor layout, this spike can generate voltages across the
LT3436 that may exceed its absolute maximum rating. A
ground plane should always be used under the switcher
circuitry to prevent interplane coupling and overall noise.
The V C and FB components should be kept as far away as
possible from the switch node. The LT3436 pinout has
been designed to aid in this. The ground for these compo-
nents should be separated from the switch current path.
Failure to do so will result in poor stability or subharmonic
like oscillation.
Board layout also has a significant effect on thermal
resistance. The exposed pad is the copper plate that runs
under the LT3436 die. This is the best thermal path for heat
out of the package. Soldering the pad onto the board will
reduce die temperature and increase the power capability
of the LT3436. Provide as much copper area as possible
around this pad. Adding multiple solder filled feedthroughs
under and around the pad to the ground plane will also
help. Similar treatment to the catch diode and inductor
terminations will reduce any additional heating effects.
D1
V OUT
SW
LT3436
HIGH
V IN
FREQUENCY
SWITCHING
C1 LOAD
PATH
GND
3436 F05
Figure 5. High Speed Switching Path
3436fa
9
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