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参数资料
| 型号： | LT3460ESC6-1#TRMPBF |
| 厂商： | Linear Technology |
| 文件页数： | 6/12页 |
| 文件大小： | 0K |
| 描述： | IC REG BOOST ADJ 0.18A SC70-6 |
| 标准包装： | 500 |
| 类型： | 升压（升压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1.26 V ~ 36 V |
| 输入电压： | 2.5 V ~ 16 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 650kHz |
| 电流 - 输出： | 180mA |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-TSSOP，SC-88，SOT-363 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | SC-70-6 |
LT3460/LT3460-1
OPERATION
V IN
5V
C1
4.7μF
OFF ON
4
5
V IN
SHDN
L1
22μH
LT3460
GND
1
SW
FB
D1
3
R2
130k
R1
15k
C F
22pF
V OUT
12V
70mA
C2
1μF
60
50
40
30
20
10
0
GAIN
PHASE
90
45
0
–45
–90
–135
–180
2
C1: TAIYO YUDEN X5R JMK212BJ475KG
C2: TAIYO YUDEN X5R EMK316BJ105
–10
–20
–225
–270
D1: CENTRAL SEMICONDUCTOR CMDSH2-3
L1: MURATA LQH32CN-220 OR EQUIVALENT
3460 F02
–30
–40
–315
–360
Figure 2. 5V to 12V Step-Up Converter
1
10 100
FREQUENCY (kHz)
1000
3460 F03
The feedback loop gain T(s) = K3 ? G P (s) ? G C (s). If it
crosses over 0dB far before f Z , the phase margin will be
Figure 3
small. Figure 3 is the Bode plot of the feedback loop gain
measured from the converter shown in Figure 2 without
the feedforward capacitor C F . The result agrees with
the previous discussion: Phase margin of about 20° is
insuf?cient.
In order to improve the phase margin, a feed-forward
capacitor C F in Figure 2 can be used.
Without the feed-forward capacitor, the transfer function
from V OUT to FB is:
60
50
40
30
20
10
0
–10
–20
–30
GAIN
PHASE
90
45
0
–45
–90
–135
–180
–225
–270
–315
FB
V OUT
=
R1
R1 + R2
–40
1
10 100
FREQUENCY (kHz)
–360
1000
3460 F04
With the feed-forward capacitor C F , the transfer function
Figure 4
=
? C F + 1
becomes:
FB
V OUT
R1
R1 + R2
?
s?
s ? R2 ? C F + 1
R1? R2
R1 + R2
The feed-forward capacitor increases the gain at high
frequency. The feedback loop therefore needs to have
enough attenuation at the switching frequency to reject
the switching noise. Additional internal compensation
components have taken this into consideration.
The feed-forward capacitor C F generates a zero and a pole.
The zero always appears before the pole. The frequency
distance between the zero and the pole is determined
only by the ratio between V OUT and FB. To give maximum
phase margin, C F should be chosen so that the midpoint
frequency between the zero and the pole is at the cross
over frequency.
With C F = 20pF, the feedback loop Bode plot is reshaped
as shown in Figure 4. The phase margin is about 60°.
For most of the applications of LT3460/LT3460-1, the
output capacitor ESR zero is at very high frequency and
can be ignored. If a low frequency ESR zero exists, for
example, when a high-ESR Tantalum capacitor is used at
the output, the phase margin may be enough even without
a feed-forward capacitor. In these cases, the feed-forward
capacitor should not be added because it may cause
the feedback loop to not have enough attenuation at the
switching frequency.
3460fb
6
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|---|---|
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| LT3461AES6#TR | 功能描述:IC REG BOOST ADJ 0.25A TSOT23-6 RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:2,500 系列:- 类型:升压（升压） 输出类型:可调式 输出数:1 输出电压:1.24 V ~ 30 V 输入电压:1.5 V ~ 12 V PWM 型:电流模式，混合 频率 - 开关:600kHz 电流 - 输出:500mA 同步整流器:无 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) 供应商设备封装:8-SOIC |
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