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参数资料
| 型号： | LT3470HDDB |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | 0.2 A SWITCHING REGULATOR, PDSO8 |
| 封装： | 3 X 2 MM, 0.75MM INCH HEIGHT, MO-229WECD-1, PLASTIC, DFN-8 |
| 文件页数： | 5/20页 |
| 文件大小： | 256K |
| 代理商： | LT3470HDDB |
13
LT3470
3470fc
SHDN
VIN
VOUT
(A)
(B)
VOUT
3470 F05
GND
SHDN
VIN
GND
C1
C2
VIAS TO FEEDBACK DIVIDER
VIAS TO LOCAL GROUND PLANE
OUTLINE OF LOCAL GROUND PLANE
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board layout. Note that large,
switched currents flow in the power switch, the internal
catch diode and the input capacitor. The loop formed by
these components should be as small as possible. Fur-
thermore, the system ground should be tied to the regu-
lator ground in only one place; this prevents the switched
current from injecting noise into the system ground.
These components, along with the inductor and output
capacitor, should be placed on the same side of the circuit
board, and their connections should be made on that layer.
Place a local, unbroken ground plane below these compo-
nents, and tie this ground plane to system ground at one
Figure 5. A Good PCB Layout Ensures Proper, Low EMI Operation
APPLICATIO S I FOR ATIO
WU
UU
location, ideally at the ground terminal of the output
capacitor C2. Additionally, the SW and BOOST nodes
should be kept as small as possible. Unshielded inductors
can induce noise in the feedback path resulting in instabil-
ity and increased output ripple. To avoid this problem, use
vias to route the VOUT trace under the ground plane to the
feedback divider (as shown in Figure 5). Finally, keep the
FB node as small as possible so that the ground pin and
ground traces will shield it from the SW and BOOST nodes.
Figure 5 shows component placement with trace, ground
plane and via locations. Include vias near the GND pin, or
pad, of the LT3470 to help remove heat from the LT3470
to the ground plane.
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相关代理商/技术参数 |
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