参数资料
型号: LT3473AEDE#TRPBF
厂商: Linear Technology
文件页数: 10/12页
文件大小: 0K
描述: IC REG BOOST ADJ 1A 12DFN
标准包装: 2,500
类型: 升压(升压)
输出类型: 可调式
输出数: 1
输出电压: 可调至 34V
输入电压: 2.2 V ~ 16 V
PWM 型: 电流模式,混合
频率 - 开关: 1.2MHz
电流 - 输出: 1A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 12-WFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 12-DFN(4x3)
LT3473/LT3473A
APPLICATIO S I FOR ATIO
between the OUT pin and ground. A ceramic capacitor with
a value of 1 μ F is a good choice. The voltage drop (PNP
V CESAT ) can be accounted for by setting the output voltage
according to the following formula:
connected to the two bases as shown in Figure 5 to
generate buffered voltage at the emitters. When sourcing
high current at low voltage, keep in mind that the NPNs
will be dissipating a fair amount of power, which must be
supplied by the DC/DC converter.
V OUT = V INT – V CESAT = V REF ? ? 1 +
? – V CESAT
?
?
R 2 ?
R 1 ?
Thermal Shutdown
The LT3473 has thermal shutdown circuitry that shuts down
Auxiliary NPN Devices (LT3473A Only)
The LT3473A has two auxiliary NPNs as shown in the
Block Diagram that can provide intermediate outputs less
than OUT. The collectors of the NPNs are connected to the
OUT pin internally. Each NPN can dissipate 100mW safely
and has a minimum beta of 60. A resistor string can be
the part when the junction temperature reaches approxi-
mately 145 ° C to protect the part from abnormal operation
with high power dissipation, such as an output short cir-
cuit or excessive power dissipation in the auxiliary NPNs.
The part will turn back on when the junction cools down to
approximately 125 ° C. If the abnormal condition remains,
the part will turn on and off while maintaining the junction
temperature within the window between 125 ° C and 145 ° C.
2 OUT
R EXT1
3 NB1
Board Layout Consideration
As with all switching regulators, careful attention must be
4
NE1
6
NE2
R EXT2
5 NB2
R EXT3
3473 F05
paid to the PCB board layout and component placement.
To maximize efficiency, switch rise and fall times are made
as short as possible. To prevent electromagnetic interfer-
ence (EMI) problems, proper layout of the high frequency
switching path is essential. The voltage signal of the SW
pin has sharp rise and fall edges. Minimize the length and
Figure 5. Auxiliary NPN Transistors in LT3473A. R EXT1 , R EXT2
and R EXT3 Set Intermediate Voltage at NE1 and NE2
area of all traces connected to the SW pin and always use
a ground plane under the switching regulator to minimize
interplane coupling. Recommended component place-
ment is shown in Figure 6.
OUT
1
12
2
11
OUT
3
4
13
10
9
1
2
8
7
5
6
8
7
3
4
9
6
5
3473 F06a
3473 F06b
Figure 6. Recommended Component Placement
3473f
10
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