LT3500
11
3500fc
VIN undervoltage detection or thermal shutdown will
set the soft-start latch, resulting in a complete soft-start
sequence.
The switch driver operates from either the VIN or BST volt-
age. An external diode and capacitor are used to generate
a drive voltage higher than VIN to saturate the output NPN
and maintain high efciency.
In addition to the switching regulator, the LT3500 contains
a NPN linear regulator with a 0.8V reference, and 13mA
current capability. The 0.8 reference will track the SS pin
OPERATION
in the same manner as the switching regulator. The linear
output can also be congured to drive an external NPN to
provide a linear regulator with higher current capability.
A power good comparator with 30mV of hysteresis trips
when both FB and LFB are above 90% of the 0.8V refer-
ence. The PG output is an open collector NPN that is off
when the output is in regulation allowing a resistor to pull
the PG pin to a desired voltage. The PG output is an open-
collector NPN that is on when the output is in regulation
providing either drive for an output disconnect transistor
or inverted power good logic.
Choosing the Output Voltage
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the 1% resis-
tors according to:
R1
=R2
VOUT1
0.8V
–1
R2 should be 10.0k or less to avoid bias current errors.
Reference designators refer to the Block Diagram in
Figure 1.
Choosing the Switching Frequency
The LT3500 switching frequency is set by resistor R5 in
Figure 1. The RT/SYNC pin is internally regulated at 1V.
Setting resistor R5 sets the current in the RT/SYNC pin
which determines the oscillator frequency as illustrated
in Figure 2.
The switching frequency is typically set as high as pos-
sible to reduce overall solution size. The LT3500 employs
techniques to enhance dropout at high frequencies but
efciency and maximum input voltage decrease due to
switching losses and minimum switch on times. The
maximum recommended frequency can be approximated
by the equation:
Frequency (Hz)
=
V
OUT1 + VD
V
IN VSW + VD
1
t
ON(MIN)
where VD is the forward voltage drop of the catch diode
(D1 Figure 1), VSW is the voltage drop of the internal
switch, and tON(MIN) is the minimum on time of the
switch, all at maximum load current.
Figure 2. Frequency vs RT/SYNC Resistance
APPLICATIONS INFORMATION
RRT/SYNC (kΩ)
0
FREQUENCY
(kHz) 1500
2000
2500
160
3500 F02
1000
500
1250
1750
2250
750
250
0
40
20
80
60
120 140
180
100
200