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参数资料
| 型号： | LT3500IMSE#TRPBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | 3.5 A SWITCHING REGULATOR, 2800 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封装： | LEAD FREE, PLASTIC, MSOP-16 |
| 文件页数： | 11/28页 |
| 文件大小： | 318K |
| 代理商： | LT3500IMSE#TRPBF |
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LT3500
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3500fc
Figure 7. Synchronous Signal Powered from Regulator’s Output
LT3500
SYNCHRONIZATION
CIRCUITRY
LDRV
PG
RT/SYNC
3500 F07
VCC
CLK
current proportional to the voltage at the VC pin. Note that
the output capacitor integrates this current, and that the
capacitor on the VC pin (CC) integrates the error amplier
output current, resulting in two poles in the loop. In
most cases a zero is required and comes from either the
output capacitor ESR or from a resistor in series with CC.
This simple model works well as long as the value of the
inductor is not too high and the loop crossover frequency
is much lower than the switching frequency. A phase lead
capacitor (CPL) across the feedback divider may improve
the transient response.
Synchronization
The RT/SYNC pin can be used to synchronize the LT3500
to an external clock source. Driving the RT/SYNC resistor
with a clock source triggers the synchronization detection
circuitry. Once synchronization is detected, the rising edge
of SW will be synchronized to the rising edge of the RT/SYNC
pin signal. An AGC loop will adjust slope compensation
to avoid subharmonic oscillation.
The synchronizing clock signal input to the LT3500 must
have a frequency between 250kHz and 2.5MHz, a duty
cycle between 20% and 80%, a low state below 0.5V and
a high state above 1.6V. Synchronization signals outside
of these parameters will cause erratic switching behavior.
The RT/SYNC resistor should be set such that the free
running frequency ((VRT/SYNC – VSYNCLO)/RRT/SYNC) is
approximately equal to the synchronization frequency. If
the synchronization signal is halted, the synchronization
detection circuitry will timeout in typically 10μs at which
time the LT3500 reverts to the free-running frequency based
on the current through RT/SYNC. If the RT/SYNC pin is held
above 1.1V at any time, switching will be disabled.
If the synchronization signal is not present during regu-
lator start-up (for example, the synchronization circuitry
is powered from the regulator output) the RT/SYNC pin
must see an equivalent resistance to ground between 15k
and 200k until the synchronization circuitry is active for
proper start-up operation.
If the synchronization signal powers up in an undetermined
state (VOL, VOH, Hi-Z), connect the synchronization clock
to the LT3500 as shown in Figure 7. The circuit as shown
will isolate the synchronization signal when the output
voltage is below 90% of the regulated output. The LT3500
will start-up with a switching frequency determined by the
resistor from the RT/SYNC pin to ground.
APPLICATIONS INFORMATION
If the synchronization signal powers up in a low impedance
state (VOL), connect a resistor between the RT/SYNC pin
and the synchronizing clock. The equivalent resistance
seen from the RT/SYNC pin to ground will set the start-up
frequency.
If the synchronization signal powers up in a high impedance
state (Hi-Z), connect a resistor from the RT/SYNC pin to
ground. The equivalent resistance seen from the RT/SYNC
pin to ground will set the start-up frequency.
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| LT3501EFE#PBF | 功能描述:IC REG BUCK ADJ 3A DL 20TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:250 系列:- 类型:降压（降压） 输出类型:固定 输出数:1 输出电压:1.2V 输入电压:2.05 V ~ 6 V PWM 型:电压模式 频率 - 开关:2MHz 电流 - 输出:500mA 同步整流器:是 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:6-UFDFN 包装:带卷 (TR) 供应商设备封装:6-SON（1.45x1） 产品目录页面:1032 (CN2011-ZH PDF) 其它名称:296-25628-2 |
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