参数资料
型号: LT3575IFE#TRPBF
厂商: Linear Technology
文件页数: 14/24页
文件大小: 0K
描述: IC REG FLYBACK ISO ADJ 16TSSOP
标准包装: 2,500
类型: 回扫,隔离
输出类型: 可调式
输出数: 1
输出电压: 可调至 60V
输入电压: 3 V ~ 40 V
PWM 型: 电流模式,混合
频率 - 开关: 1MHz
电流 - 输出: 2.5A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 16-TSSOP-EP
配用: 732-3306-ND - BOARD EVAL FOR LT3575
相关产品: 732-2669-2-ND - TRANS FLYBACK LT3748 20UH SMD
732-2669-6-ND - TRANS FLYBACK LT3748 20UH SMD
732-2668-6-ND - TRANS FLYBACK LT3748 14UH SMD
732-2667-6-ND - TRANS FLYBACK LT3748 500UH SMD
732-2666-6-ND - TRANS FLYBACK LT3748 12UH SMD
732-2665-6-ND - TRANS FLYBACK LT3748 12UH SMD
732-2664-6-ND - TRANS FLYBACK LT3748 15UH SMD
732-2663-6-ND - TRANS FLYBACK LT3748 15UH SMD
732-2662-6-ND - TRANS FLYBACK LT3748 8UH SMD
732-2661-6-ND - TRANS FLYBACK LT3748 8UH SMD
更多...
LT3575
APPLICATIONS INFORMATION
Secondary Leakage Inductance
In addition to the previously described effects of leakage
inductance in general, leakage inductance on the secondary
in particular exhibits an additional phenomenon. It forms
an inductive divider on the transformer secondary that
effectively reduces the size of the primary-referred
?yback pulse used for feedback. This will increase the
output voltage target by a similar percentage. Note that
unlike leakage spike behavior, this phenomenon is load
independent. To the extent that the secondary leakage
inductance is a constant percentage of mutual inductance
(over manufacturing variations), this can be accommodated
The Switch Current Limit vs R ILIM plot in the Typical
Performance Characteristics section depicts a more
accurate current limit.
Undervoltage Lockout (UVLO)
The SHDN /UVLO pin is connected to a resistive voltage
divider connected to V IN as shown in Figure 8. The voltage
threshold on the SHDN /UVLO pin for V IN rising is 1.22V.
To introduce hysteresis, the LT3575 draws 2.8μA from the
SHDN /UVLO pin when the pin is below 1.22V. The hysteresis
is therefore user-adjustable and depends on the value of
R1. The UVLO threshold for V IN rising is:
by adjusting the R FB /R REF resistor ratio.
Winding Resistance Effects
V IN ( UVLO , RISING ) =
1 . 22 V ? (R1 + R2)
R 2
+ 2 . 8 μA ? R 1
Resistance in either the primary or secondary will reduce
The UVLO threshold for V IN falling is:
overall efficiency (P OUT / P IN ). Good output voltage
regulation will be maintained independent of winding
resistance due to the boundary mode operation of the
V IN ( UVLO , FALLING ) =
1 . 22 V ? (R1 + R2)
R 2
LT3575.
Bi?lar Winding
A bi?lar, or similar winding technique, is a good way to
minimize troublesome leakage inductances. However,
remember that this will also increase primary-to-secondary
capacitance and limit the primary-to-secondary breakdown
voltage, so, bi?lar winding is not always practical. The
Linear Technology applications group is available and
extremely quali?ed to assist in the selection and/or design
To implement external run/stop control, connect a small
NMOS to the UVLO pin, as shown in Figure 8. Turning the
NMOS on grounds the UVLO pin and prevents the LT3575
from operating, and the part will draw less than a 1μA of
quiescent current.
V IN
R1
SHDN /UVLO
of the transformer.
LT3575
R2
RUN/STOP
CONTROL
(OPTIONAL)
Setting the Current Limit Resistor
The maximum current limit can be set by placing a resistor
between the R ILIM pin and ground. This provides some
?exibility in picking standard off-the-shelf transformers that
GND
3575 F08
Figure 8. Undervoltage Lockout (UVLO)
may be rated for less current than the LT3575’s internal
power switch current limit. If the maximum current limit
is needed, use a 10k resistor. For lower current limits, the
following equation sets the approximate current limit:
R ILIM = 65 ? 10 3 ( 3 . 5 A ? I LIM ) + 10 k
3575f
14
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