参数资料
型号: LT3580EMS8E#PBF
厂商: Linear Technology
文件页数: 15/28页
文件大小: 0K
描述: IC REG BOOST INV SEPIC 2A 8MSOP
标准包装: 50
类型: 升压(升压),反相,Sepic
输出数: 1
输入电压: 2.5 V ~ 32 V
PWM 型: 电流模式
频率 - 开关: 200kHz ~ 2.5MHz
电流 - 输出: 2A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)裸露焊盘
包装: 管件
供应商设备封装: 8-MSOP-EP
产品目录页面: 1332 (CN2011-ZH PDF)
LT3580
APPLICATIONS INFORMATION
Average Input Current: I IN = OUT OUT
Base Drive Loss (DC): P BDC =
so they should not be used for calculating efficiency in
discontinuous mode or at light load currents.
V ?I
V IN ? η
Switch I 2 R Loss: P SW = (DC)(I IN ) 2 (R SW )
Base Drive Loss (AC): P BAC = 13n(I IN )(V OUT )(f)
(V IN )(I IN )(DC)
50
Input Power Loss: P INP = 7mA(V IN )
where:
R SW = switch resistance (typically 200m Ω at 1.5A)
DC = duty cycle (see the Power Switch Duty Cycle sec-
tion for formulas)
η = power conversion efficiency (typically 88% at high
currents)
Example: boost configuration, V IN = 5V, V OUT = 12V,
I OUT = 0.5A, f = 1.25MHz, V D = 0.5V:
I IN = 1.36A
DC = 61.5%
P SW = 228mW
P BAC = 270mW
P BDC = 84mW
P INP = 35mW
Total LT3580 power dissipation (P TOT ) = 617mW
Thermal resistance for the LT3580 is influenced by the pres-
ence of internal, topside or backside planes. To calculate
die temperature, use the appropriate thermal resistance
number and add in worst-case ambient temperature:
T J = T A + θ JA ? P TOT
where T J = junction temperature, T A = ambient tempera-
ture, θ JA = 43°C/W for the 3mm × 3mm DFN package and
35°C/W to 40°C/W for the MSOP Exposed Pad package.
V IN Ramp Rate
While initially powering a switching converter application,
the V IN ramp rate should be limited. High V IN ramp rates can
cause excessive inrush currents in the passive components
of the converter. This can lead to current and/or voltage
overstress and may damage the passive components or
the chip. Ramp rates less than 500mV/μs, depending on
component parameters, will generally prevent these issues.
Also, be careful to avoid hot-plugging. Hot-plugging occurs
when an active voltage supply is “instantly” connected or
switched to the input of the converter. Hot-plugging results
in very fast input ramp rates and is not recommended.
Finally, for more information, refer to Linear application
note AN88, which discusses voltage overstress that can
occur when an inductive source impedance is hot-plugged
to an input pin bypassed by ceramic capacitors.
Layout Hints
As with all high frequency switchers, when considering
layout, care must be taken to achieve optimal electrical,
thermal and noise performance. One will not get adver-
tised performance with a careless layout. For maximum
efficiency, switch rise and fall times are typically in the
5ns to 10ns range. To prevent noise, both radiated and
conducted, the high speed switching current path, shown in
Figure 8, must be kept as short as possible. This is imple-
mented in the suggested layout of a boost configuration in
Figure 9. Shortening this path will also reduce the parasitic
trace inductance. At switch-off, this parasitic inductance
produces a flyback spike across the LT3580 switch. When
operating at higher currents and output voltages, with poor
layout, this spike can generate voltages across the LT3580
that may exceed its absolute maximum rating. A ground
plane should also be used under the switcher circuitry to
prevent interplane coupling and overall noise.
The VC and FB components should be kept as far away
as practical from the switch node. The ground for these
components should be separated from the switch cur-
rent path. Failure to do so can result in poor stability or
subharmonic oscillation.
P TOT is calculated above.
3580fg
15
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