参数资料
型号: LT3640EFE#PBF
厂商: Linear Technology
文件页数: 19/24页
文件大小: 0K
描述: IC REG BUCK FIX/ADJ DL 28TSSOP
标准包装: 50
类型: 降压(降压)
输出类型: 两者兼有
输出数: 2
输出电压: 1.8V,3.3V,可调
输入电压: 2.5 V ~ 35 V
PWM 型: 电流模式,混合
频率 - 开关: 500kHz ~ 2MHz
电流 - 输出: 1.1A,1.3A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.173",4.40mm 宽)裸露焊盘
包装: 管件
供应商设备封装: 28-TSSOP 裸露焊盘
LT3640
APPLICATIONS INFORMATION
t RST POR ? 37 ? 10 6 ? ?
= C
WD STARTS
pull-ups eliminate the need for external pull-ups when
the rise time of these pins is not critical. The open-drain
configuration allows wired-OR connections.
The two power-on reset timers share one oscillator. The
power-on reset timeout period, t RST (64 cycles on the
CPOR pin), which is the same for the two channels, can
be programmed by connecting a capacitor, C POR , between
the CPOR pin and ground:
? s ?
? F ?
The accuracy of the watchdog timer will be limited by
the accuracy and temperature coefficient of the capacitor
C WDT . Extra parasitic capacitance on the CWDT pin, such
as probe capacitance, can affect the watchdog timer.
CWDT
CPOR
64 CYCLES 64 CYCLES
FB2
FB1
For example, using a capacitor value of 8.2nF gives a
303ms reset timeout period. The accuracy of t RST will be
limited by the accuracy and temperature coefficient of the
capacitor CPOR. Extra parasitic capacitance on the CPOR
pin, such as probe capacitance, can affect t RST .
Watchdog
The WDE pin is the enable pin for the watchdog. As soon
as both RST1 and RST2 are released, the watchdog starts
a delay period, t DLY , during which the input signal at the
WDI pin is ignored for higher reliability. After the delay
period, the watchdog starts detecting falling edges on the
WDI pin. If the time between any two WDI falling edges is
shorter than the watchdog lower boundary, t WDL , or longer
than the watchdog upper boundary, t WDU , the WDO pin
is pulled down for a period of t RST , which is the same as
the power-on reset timeout period. When the WDO pin is
released, the watchdog again starts the delay period.
The WDO is open-drain output with weak internal pull-up,
similar to the RST pins.
The delay period corresponding to 33 cycles on CWDT, the
watchdog lower boundary (4 cycles on CWDT), and the
watchdog upper boundary (64 cycles on CWDT) are all
related and set by a capacitor, C WDT , between the CWDT
pin and ground:
RST1
RST2
CWDT
CPOR
WDI
WDO
CWDT
CPOR
WDI
WDO
20ms/DIV
(9a)
1ms/DIV
(9b)
50ms/DIV
3640 F09a
3640 F09b
3640 F09c
= t
t DLY WDU ? ?
t WDL = WDU
t WDU WDT ? 37 ? 10 6 ? ?
= C
t
16
? 33 ?
? 64 ? ?
? s ?
? F ?
(9c)
Figure 9. Power-On Reset and Watchdog Timing
3640f
  
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