参数资料
型号: LT3681EDE#TRPBF
厂商: Linear Technology
文件页数: 15/24页
文件大小: 0K
描述: IC REG BUCK ADJ 2A 14DFN
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.27 V ~ 20 V
输入电压: 3.6 V ~ 34 V
PWM 型: 电流模式,混合
频率 - 开关: 300kHz ~ 2.8MHz
电流 - 输出: 2A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 14-WFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 14-DFN-EP(4x3)
LT3681
APPLICATIONS INFORMATION
6.0
5.5
5.0
4.5
4.0
3.5
V OUT = 3.3V
T A = 25 C
L = 4.7
f = 800 kHz
Synchronization
The internal oscillator of the LT3681 can be synchronized
to an external 275kHz to 475kHz clock by using a 5pF
to 20pF capacitor to connect the clock signal to the RT
pin. The resistor tying the RT pin to ground should be
3.0
2.5
2.0
0.001
TO START (RUN/SS = V IN )
TO START (RUN/SS CONTROL)
TO RUN
0.01 0.1 1
10
chosen such that the LT3681 oscillates 20% lower than
the intended synchronization frequency (see Setting the
Switching Frequency section).
LOAD CURRENT (A)
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
V OUT = 5.0V
T A = 25 C
L = 4.7
f = 800 kHz
TO START (RUN/SS = V IN )
TO START (RUN/SS CONTROL)
TO RUN
The LT3681 should not be synchronized until its output
is near regulation as indicated by the PG ?ag. This can be
done with the system microcontroller/microprocessor or
with a discrete circuit by using the PG output. If a sync
signal is applied while the PG is low, the LT3681 may
exhibit erratic operation.
When applying a sync signal, positive clock transitions
reset LT3681’s internal clock and negative transitions
2.0
0.001
0.01
0.1
1
10
initiate a switch cycle. The amplitude of the sync signal
LOAD CURRENT (A)
3681 F06
must be at least 2V. The sync signal duty cycle can range
Figure 6. The Minimum Input Voltage Depends on
Output Voltage, Load Current and Boost Circuit
from 5% up to a maximum value given by the following
equation:
DC SYNC ( ) = ? 1 –
?
Soft-Start
The RUN/SS pin can be used to soft-start the LT3681,
MAX
?
V OUT + V D ?
?
V IN – V SW + V D ?
– f SW ? 6 00ns
reducing the maximum input current during start-up.
The RUN/SS pin is driven through an external RC ?lter to
create a voltage ramp at this pin. Figure 7 shows the start-
up and shut-down waveforms with the soft-start circuit.
By choosing a large RC time constant, the peak start-up
current can be reduced to the current that is required to
regulate the output, with no overshoot. Choose the value
of the resistor so that it can supply 20μA when the RUN/SS
pin reaches 2.3V.
where V OUT is the programmed output voltage, V D is the
diode forward drop, V IN is the typical input voltage, V SW
is the switch drop, and f SW is the desired switching fre-
quency. For example, a 24V input to 5V output at 300kHz
can be synchronized to a square wave with a maximum
duty cycle of 60%. For some applications, such as 12V IN
to 5V OUT at 350kHz, the maximum allowable sync duty
cycle will be less than 50%. If a low duty cycle clock cannot
be obtained from the system, then a one-shot should be
used between the sync signal and the LT3681. The value
RUN
15k
I L
1A/DIV
of the coupling capacitor which connects the clock signal
to the RT pin should be chosen based on the clock signal
amplitude. Good starting values for 3.3V and 5V clock
0.22 μ F
RUN/SS
GND
V RUN/SS
2V/DIV
signals are 10pF and 5pF, respectively. These values should
be tested and adjusted for each individual application to
V OUT
2V/DIV
assure reliable operation.
2ms/DIV
3681 F07
Figure 7. To Soft-Start the LT3681, Add a Resistor
and Capacitor to the RUN/SS Pin
3681f
15
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