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| 型号： | LT3689IUD-5#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 25/34页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK 5V 0.7A 16QFN |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 5V |
| 输入电压： | 3.6 V ~ 36 V |
| PWM 型： | 电流模式，Burst Mode? |
| 频率 - 开关： | 500kHz ~ 2MHz |
| 电流 - 输出： | 700mA |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-QFN-EP（3x3） |
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LT3689/LT3689-5
APPLICATIONS INFORMATION
C WDT = t WDU ? 55
t WDL =
? t WDU
C WDT = t WDL ?
capacitorleakage(thenominalchargingcurrentis2μA)
and capacitor tolerance. A low leakage ceramic capacitor
is recommended.
Selecting the Watchdog Timing Capacitor
The watchdog timeout period is adjustable and can be
optimized for software execution. The watchdog upper
boundary timeout period, t WDU is adjusted by connect-
ing a capacitor, C WDT , between the C WDT pin and ground.
Given a specified watchdog timeout period, the capacitor
is determined by:
pF
ms
This equation is accurate for upper boundary periods of
20ms, or greater. The watchdog lower boundary period
(t WDL ) has a fixed relationship to t WDU for a given capaci-
tor. The t WDL period is related to t WDU by the following:
1
31
In addition, the following equation can be used to calculate
the watchdog lower boundary period for a given C WDT
capacitor value.
1.7nF
ms
These lower boundary period equations are accurate for a
t WDL of 3ms, or greater. To program faster t WDU and t WDL
periods, see the Watchdog Upper and Lower Boundary
Periods vs Capacitance graphs in the Typical Performance
Characteristics section.
Leaving the C WDT pin unconnected will generate a minimum
watchdog timeout of approximately 200μs. Maximum
timeout is limited by the largest available low leakage
capacitor. The accuracy of the timeout period will be af-
fected by capacitor leakage (the nominal charging current
is 2μA) and capacitor tolerance. A low leakage ceramic
capacitor is recommended.
Time Charts for the Power-On-Reset and
Watch Dog Timers
The watchdog timer monitors proper operation of the
microprocessor. During the start-up sequence of the mi-
croprocessor, there are fixed requirements for the watch
dog input (WDI) in order to keep the WDO pin from flag-
ging a fault.
Requirements for the watch dog input in window mode
(W/T = Low) are best understood by looking at Figure 13.
In window mode, the WDI pin detects falling edges. These
edges are ignored until the power-on-reset timer expires,
and the CWDT pin has risen above 0.2V for the first time,
as shown in Figure 13a. After that time, there must be a
falling edge on the WDI pin before the watchdog timer
expires, which will happen within t WDU (a minimum of
17ms while using 1000pF for CWDT). After this first valid
falling edge, subsequent edges must follow the timing
sequence outlined in Figure 13b. Each subsequent edge
must occur after t WDL (a maximum of 785μs while using
1000pF for CWDT) and before t WDU .
If there is a timing fault, the WDO pin will flag low, and will
initiate a restart sequence using the power-on-reset timer,
as shown in Figure 13c. The RST pin will remain high,
however. WDI edges are ignored until the power-on-reset
timer expires, and the CWDT pin has risen above 0.2V. After
that time, there must be a falling edge on the WDI pin be-
fore the watchdog timer expires, which will happen within
t WDU . After this first valid falling edge, subsequent edges
must follow the timing sequence outlined in Figure 13b.
Requirements for the watch dog input in timer mode (W/T
= High) are best understood by looking at Figure 14. In
timer mode, the WDI pin detects rising and falling edges.
These edges are ignored until the power-on-reset timer
expires, and the CWDT pin has risen above 0.2V for the
first time, as shown in Figure 14a. After that time, there
must be an edge on the WDI pin before the watchdog
timer expires, which will happen within t WDU (a minimum
of 17ms while using 1000pF for CWDT). After this first
edge, subsequent edges must follow the timing sequence
outlined in Figure 14b. Each subsequent edge must occur
before t WDU .
3689fe
For more information www.linear.com/LT3689
25
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LT3689IUD-PBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:700mA Step-Down Regulator with Power-On Reset and Watchdog Timer |
| LT3689IUD-TRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:700mA Step-Down Regulator with Power-On Reset and Watchdog Timer |
| LT3690 | 制造商:LINER 制造商全称:Linear Technology 功能描述:36V, 4A, 1.5MHz Synchronous Step-Down Switching Regulator |
| LT3690EUFE#PBF | 功能描述:IC REG BUCK SYNC ADJ 4A 26QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:250 系列:- 类型:降压（降压） 输出类型:固定 输出数:1 输出电压:1.2V 输入电压:2.05 V ~ 6 V PWM 型:电压模式 频率 - 开关:2MHz 电流 - 输出:500mA 同步整流器:是 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:6-UFDFN 包装:带卷 (TR) 供应商设备封装:6-SON（1.45x1） 产品目录页面:1032 (CN2011-ZH PDF) 其它名称:296-25628-2 |
| LT3690EUFE#TRPBF | 功能描述:IC REG BUCK SYNC ADJ 4A 26QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 设计资源:Design Support Tool 标准包装:1 系列:- 类型:升压（升压） 输出类型:固定 输出数:1 输出电压:3V 输入电压:0.75 V ~ 2 V PWM 型:- 频率 - 开关:- 电流 - 输出:100mA 同步整流器:是 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:SOT-23-5 细型，TSOT-23-5 包装:剪切带 (CT) 供应商设备封装:TSOT-23-5 其它名称:AS1323-BTTT-30CT |
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