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参数资料
| 型号： | LT3692IUH#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | 5.8 A DUAL SWITCHING CONTROLLER, 2750 kHz SWITCHING FREQ-MAX, PQCC32 |
| 封装： | 5 X 5 MM, LEAD FREE, PLASTIC, MO-220WHHD, QFN-32 |
| 文件页数： | 4/36页 |
| 文件大小： | 526K |
| 代理商： | LT3692IUH#PBF |
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LT3692
12
3692f
BLOCK DIAGRAM
A comparator with a threshold of 720mV and 60mV of
hysteresis is provided for detecting error conditions. The
CMPO output is an open-collector NPN that is off when
the CMPI pin is above the threshold allowing a resistor
to pull the CMPO pin to a desired voltage.
The voltage present at the TJ pin is proportional to the
junction temperature of the LT3692. The TJ pin will be
250mV for a die temperature of 25°C and will have a
slope of 10mV/°C.
APPLICATIONS INFORMATION
Choosing the Output Voltage
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the 1% resis-
tors according to:
R1
= R2
VOUT
0.806
– 1
R2 should be 10k or less to avoid bias current errors. Ref-
erence designators refer to the Block Diagram in Figure 1.
Choosing the Switching Frequency
The LT3692 switching frequency is set by resistor R3 in
Figure 1. The RT/SYNC pin is driven by a 12A current
source. Setting resistor R3 sets the voltage present at
the RT/SYNC pin which determines the master oscillator
frequency as illustrated in Figure 2. A 0V to 2.5V square
wave with the same frequency as the master oscillator
and in phase with channel 1 is output via the CLKOUT pin.
The CLKOUT signal can be used to synchronize multiple
switching regulators.
Toalleviatedutycyclerestrictionsduetominimumswitch-
on times, channel 1’s switching frequency can be divided
fromthemasterclockby1,2,4or8determinedbyresistor
RDIV in Figure 1. Channel 2’s switching frequency is not
affected by the DIV pin. The DIV pin is driven by a 12A
current source. Setting resistor RDIVsetsthevoltagepres-
ent at the DIV pin which determines the divisor as shown
in Table 1. The DIV pin doesn’t have any input hysteresis
near the ratio thresholds.
Table 1. Channel 1 Divisor vs VDIV
DIV VOLTAGE
FREQUENCY RATIO
RDIV
VDIV < 0.5V
1
0
0.5V < VDIV < 1.0V
2
62k
1.0V < VDIV < 1.5V
4
100k
1.5V < VDIV
8
150k
The switching frequency is typically set as high as pos-
sible to reduce overall solution size. The LT3692 employs
techniques to enhance dropout at high frequencies but
efficiency and maximum input voltage decrease due to
switching losses and minimum switch on times.
The maximum recommended frequency can be approxi-
mated by the equation:
Frequency (Hz)
=
VOUT + VD
VIN – VSW + VD
1
tON(MIN)
whereVDistheforwardvoltagedropofthecatchdiode(D1
Figure 2), VSW is the voltage drop of the internal switch,
and tON(MIN) in the minimum on-time of the switch.
The following example along with the data in Table 2
illustrates the trade-offs of switch frequency selection for
a single input voltage system.
Figure 2. Switching Frequency vs RT/SYNC Resistance
RESISTANCE (k)
0
FREQUENCY
(kHz)
500
1500
2000
2500
20
40 50
90
3692 F02
1000
10
30
60 70 80
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