参数资料
型号: LT3710EFE#TRPBF
厂商: Linear Technology
文件页数: 9/12页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 16-TSSOP
标准包装: 2,500
PWM 型: 电流/电压模式
输出数: 2
频率 - 最大: 340kHz
占空比: 90%
电源电压: 8 V ~ 24 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 带卷 (TR)
LT3710
APPLICATIO S I FOR ATIO
V OUT2 ? ( 1 ? D 2 )
2 ? I LMAX 2
? I LMAX
? V OUT ≈ ? I L ? ESR +
?
8 fC OUT ?
Output Inductor Selection
The key parameters for choosing the inductor include
inductance, RMS and saturation current ratings and DCR.
The inductance must be selected to achieve a reasonable
value of ripple current, which is determined by:
? I L =
f ? L
Typically, the inductor ripple current is designed to be
20% to 40% of the maximum output current.
The RMS current rating must be high enough to deliver the
maximum output current. A sufficient saturation current
rating should prevent the inductor core from saturating.
These two current ratings can be determined by:
I RMS ≥ I O +
12
I SAT ≥ I O +
2
where I O is the maximum output current and ? I LMAX is the
maximum peak-to-peak inductor ripple current.
To optimize the efficiency, we usually choose the inductor
with the minimum DCR if the inductance and current
ratings are the same.
Power MOSFET Selection
The LT3710 drives two external N-channel MOSFETs to
deliver high currents at high efficiency. The gate drive
voltage is typically 6.5V. The key parameters for choos-
ing MOSFETs include drain to source voltage rating V DSS
and R DS(ON) at 6.5V gate drive. Note that the transformer
secondary voltage waveform will overshoot at its rising
edge due to the ringing between transformer leakage
inductance and parasitic capacitance. The V DSS of both
top and bottom MOSFETs must be sufficiently higher
than the maximum overshoot. It is recommended that an
RC snubber or a voltage clamping circuitry be placed
across the transformer secondary winding to limit the V S
overshoot.
The R DS(ON) of the MOSFETs should be selected to deliver
the required current at the desired efficiency as well as to
meet the thermal requirement of the MOSFET package.
The conduction power losses of the MOSFETs are:
P M1 ? I O2 ? R DS(ON)M1 ? D2
P M2 ? I O2 ? R DS(ON)M2 ? (1 – D2)
where I O is the maximum output current of LT3710 circuit,
R DS(ON)M1 and R DS(ON)M2 are the on-resistance for the top
and bottom MOSFETs, respectively. The R DS(ON) must be
determined with 6.5V gate drive and the expected operat-
ing temperature.
A good number of high performance power MOSFET
selections are available from Siliconix, International Rec-
tifier and Fairchild. If the V DSS and R DS(ON) ratings are the
same, the MOSFETs with the lowest gate charge Q G should
be chosen to minimize the power loss associated with the
MOSFET gate drives, the switching transitions and the
controller bias supply.
Output Capacitor Selection
The selection of the output capacitor is determined by the
output ripple and load transient requirements. In low
output voltage applications, always choose capacitors
with low ESR. The output ripple voltage is approximated
by:
? 1 ?
?
where ? I L is the inductor peak-to-peak ripple current.
A partial list of low ESR high performance capacitor types
includes SP capacitors from Panasonic and Cornell Dubilier,
POSCAPs and OS-CON capacitors from Sanyo, T510 and
T520 surface mount capacitors from Kemet.
Design Example
Figure 3 shows an application example for the LT3710. It
is a dual output, high efficiency, isolated DC/DC power
supply with 36V to 72V input, 3.3V/10A and 1.8V/10A
outputs. The basic power stage topology is a 2-transistor
3710f
9
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