参数资料
型号: LT3742EUF#PBF
厂商: Linear Technology
文件页数: 10/26页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 24-QFN
标准包装: 91
系列: PolyPhase®
PWM 型: 电流模式
输出数: 2
频率 - 最大: 560kHz
占空比: 100%
电源电压: 4 V ~ 30 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 24-WFQFN 裸露焊盘
包装: 管件
产品目录页面: 1332 (CN2011-ZH PDF)
LT3742
APPLICATIONS INFORMATION
Power Good Indicators
The PG pin is the open-collector output of an internal
window comparator that is pulled low whenever the FB
pin is not within ±10% of the 800mV internal reference
voltage. Tie the PG pin to any supply less than 30V with
a pull-up resistor that will supply less than 200μA. This
pin will be open when the LT3742 is placed in shutdown
mode regardless of the voltage at the FB pin. The power
good indication is valid only when the LT3742 is enabled
(RUN/SS is high) and V IN is 4V or greater.
LT3742
Output Sequencing and Tracking
The RUN/SS and PG pins can be used together to sequence
the two outputs of the LT3742. Figure 3 shows three
circuits to do this. For the first two cases, controller 1
starts first.
In Figure 2a, controller 2 turns on only after controller
1 has reached within 10% of its final regulation voltage.
A larger value for the soft-start capacitor on RUN/SS2
will provide additional delay between the outputs. One
SHDN
4.7nF
4.7nF
RUN/SS1
PG1
RUN/SS2
SHDN (REFERENCE)
V OUT1
5V/DIV
V OUT2
10V/DIV
5ms/DIV
3742 F02a
Figure 2a. Supply Sequencing with Controller 2 Delayed Until After Controller 1 is in Regulation
LT3742
SHDN
4.7nF
10nF
RUN/SS1
RUN/SS2
SHDN (REFERENCE)
V OUT1
5V/DIV
V OUT2
10V/DIV
5ms/DIV
3742 F02b
Figure 2b. Supply Sequencing with Controller 2 Having a Fixed Delay Relative to Controller 1
LT3742
SHDN
10nF
RUN/SS1
RUN/SS2
SHDN (REFERENCE)
V OUT1
5V/DIV
V OUT2
10V/DIV
5ms/DIV
3742 F02c
Figure 2c. Both Conditions Start Up Together with Ratiometic Tracking
3742fa
10
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