参数资料
型号: LT3742EUF#PBF
厂商: Linear Technology
文件页数: 6/26页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 24-QFN
标准包装: 91
系列: PolyPhase®
PWM 型: 电流模式
输出数: 2
频率 - 最大: 560kHz
占空比: 100%
电源电压: 4 V ~ 30 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 24-WFQFN 裸露焊盘
包装: 管件
产品目录页面: 1332 (CN2011-ZH PDF)
LT3742
PIN FUNCTIONS
G1, G2 (Pins 1, 6): Gate Drives. These pins provide high
current gate drive for the external N-channel MOSFETs.
These pins are the outputs of floating drivers whose volt-
age swings between the BIAS and SW pins.
V IN (Pin 2): Input Voltage. This pin supplies current to the
internal circuitry of the LT3742. This pin must be locally
bypassed with a capacitor.
UVLO (Pin 3): Undervoltage Lockout. Do not leave this
pin open ; connect it to V IN if not used. A resistor divider
connected to V IN is tied to this pin to program the mini-
mum input voltage at which the LT3742 will operate. When
this pin is less than 1.25V, the controllers are disabled
(the RUN/SS pins are still used to turn on each switching
regulator). Once this pin drops below 1.25V, a 3μA current
sink draws current into the pin to provide programmable
hysteresis for UVLO.
BIAS (Pin 4): Bias for Gate Drive. This pin provides a bias
voltage higher than the input voltage to drive the external
N-channel MOSFETs. The voltage on this pin is regulated
to V IN + 7V.
SWB (Pin 5): Bias Regulator Switch. This is the collec-
tor of an internal NPN switch used to generate the bias
voltage to provide gate drive for the external N-channel
MOSFETs.
RUN/SS1, RUN/SS2 (Pins 16, 15): Run/Soft-Start Pins.
These pins are used to shut down each controller. They
also provide a soft-start function with the addition of an
external capacitor. To shut down any regulator, pull the
RUN/SS pin to ground with an open-drain or open-col-
lector device. If neither feature is used, leave these pins
unconnected.
PG1, PG2 (Pins 17, 14): Power Good. These pins are
open-collector outputs of internal comparators. PG remains
low until the FB pin is within 90% of the final regulation
voltage. As well as indicating output regulation, the PG
pins can be used to sequence the switching regulators.
The PG outputs are valid when V IN is greater than 4V
and either of the RUN/SS pins is high. The power good
comparators are disabled in shutdown. If not used, these
pins should be left unconnected.
V C1 , V C2 (Pins 18, 13): Control Voltage and Compensation
Pins for Internal Error Amplifiers. Connect a series RC
from these pins to ground to compensate each switching
regulator loop.
FB1, FB2 (Pins 19, 12): Feedback Pins. The LT3742
regulates these pins to 800mV. Connect the feedback
resistors to this pin to set the output voltage for each
switching regulator.
SENSE1 – , SENSE2 – (Pins 20, 11): Negative Current Sense
Inputs. These pins (along with the SENSE + pins) are used to
sense the inductor current for each switching regulator.
SENSE1 + , SENSE2 + (Pins 21, 10): Positive Current Sense
Inputs. These pins (along with the SENSE – pins) are used to
sense the inductor current for each switching regulator.
SW1, SW2 (Pins 24, 7): Switch Nodes. These pins connect
to the source of the external N-channel MOSFETs and to
the external inductors and diodes.
Exposed Pad (Pin 25): Ground. The Exposed Pad of the
package provides both electrical contact to ground and
good thermal contact to the printed circuit board. The
Exposed Pad must be soldered to the circuit board to
ensure proper operation.
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