参数资料
型号: LT3742EUF#TRPBF
厂商: Linear Technology
文件页数: 18/26页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 24-QFN
标准包装: 2,500
系列: PolyPhase®
PWM 型: 电流模式
输出数: 2
频率 - 最大: 560kHz
占空比: 100%
电源电压: 4 V ~ 30 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 24-WFQFN 裸露焊盘
包装: 带卷 (TR)
LT3742
APPLICATIONS INFORMATION
Bias Supply Considerations
The LT3742 uses an internal boost regulator to provide a
bias rail for enhancement of the external MOSFETs. This
bias rail is regulated to V IN + 7V and must be in regula-
tion before either controller is allowed to start switching.
As this is a high speed switching regulator, standard
procedures must be followed regarding placement of the
external components. The SWB node should be kept small
to reduce EMI effects and the bias decoupling capacitor
(C BIAS ) should be kept close to the BIAS pin and V IN . A
slight surplus of power is available from this supply and
it can be tapped after stringent engineering evaluation.
PC Board Layout Considerations
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement.
? Place the power components close together with short
and wide interconnecting traces. The power compo-
nents consist of the top MOSFETs, catch diodes and
the inductors C IN and C OUT . One way to approach this
is to simply place them on the board first.
? Similar attention should be paid to the power compo -
nents that make up the boost converter. They should also
be placed close together with short and wide traces.
? Always use a ground plane under the switching regulator
to minimize interplane coupling.
? Minimize the parasitic inductance in the loop of C IN ,
MOSFET and catch diode, which carry large switching
currents.
? Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI low.
? Use planes for V IN and V OUT to maintain good voltage
filtering and to keep power losses low. Unused areas
can be filled with copper and connect to any DC node
(V IN , V OUT , GND).
? Place CB close to BIAS pin and input capacitor.
? Keep the high dv/dt nodes (SW1, SW2, G1, G2, C IN1 ,
C IN2 , SWB) away from sensitive small-signal nodes.
Demo board gerber files are available to assist with a
reliable layout. It will be difficult to achieve data sheet
performance specifications with improper layout.
3742fa
18
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