参数资料
型号: LT3745EUJ#PBF
厂商: Linear Technology
文件页数: 14/28页
文件大小: 0K
描述: IC LED DVR 16CH 50MA 40-QFN
标准包装: 61
恒定电流:
拓扑: PWM,降压(降压)
输出数: 16
内部驱动器:
类型 - 主要: 背光,通用
类型 - 次要: 颜色
频率: 200kHz ~ 1MHz
电源电压: 6 V ~ 55 V
输出电压: 36V
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 管件
工作温度: -40°C ~ 125°C
LT3745
OPERATION
the clock skew between the SCKI and SDI signals, which
usually requires the customer end to balance it. Since both
the SDI and SDO signals require the same SCKI signal to
send and receive, the propagation delay between the SDI
and SDO signals limits the number of chips in cascade
and the series data interface clock frequency.
The novel 6-wire topology eliminates the need for global
routing and buffer insertion for the LDI and SCKI signals.
Instead, it provides the LDO and SCKO signals along with
the SDO signal to drive the next chip. The skew inside the
chip among the LDI, SCKI, and SDI signals is balanced
internally. The skew outside the chip among the LDO, SCKO,
and SDO signals can be easily balanced by parallel routing
these three signals between chips. The SDI signal is sent
with the SCKI signal, and the SDO signal is received with the
SCKO signal. A slight duty cycle change between the SCKI
and SCKO signals may occur due to the process variation,
supply voltage and operating temperature. This duty cycle
change results from the difference in propagation delays of
the positive and negative edges of the SCKI/SCKO signals
and will affect the maximum number of cascadable chips,
depending on the SCKI speed. In summary, the 6-wire
topology extends the maximum number of cascadable
chips, boosts the series data interface clock frequency,
eliminates the need for buffer insertion for global signals,
and offers an easy PCB layout. In a low-speed application
with a small number of cascaded chips, the 6-wire topol-
ogy can be simplified to the 4-wire topology by ignoring
the LDO and SCKO outputs.
Figure 2 shows two serial data input SDI frames (GS frame
and DC frame) and one serial data output SDO frame (status
frame). All the frames have the same 194-bit in length and
are transmitted with the MSB first and the LSB last. The SDI
frames are sent with the SCKI signal and the SDO frame is
received with the SCKO signal. The C0 bit (frame select)
determines any SDI frame to be either a GS frame (C0 = 0)
or a DC frame (C0 = 1), and the C1 bit (EN) enables (C1 = 1)
or disables (C1 = 0) all the LED channels. The status frame
reads back the T SET pin resistor-programmable over-
temperature flag and individual open/short LED fault flags,
as well as the individual 6-bit DC setting.
Inside the part, there are one 194-bit shift register
SR[0:193], one 1-bit frame select (FS) register, one 1-bit
enable LED channel (EN) register, sixteen 12-bit grayscale
(GS) registers, sixteen 6-bit dot correction (DC) registers,
one 1-bit over temperature (OT) flag register, and sixteen
1-bit LED fault flag registers. The input of the 194-bit shift
register, i.e., the input of the first bit SR[0], is connected
to the SDI signal. The output of the 194-bit shift register,
i.e., the output of the last bit SR[193] is connected to the
SDO signal. The SCKI signal shifts the SDI frame (GS or
DC frame) in and the SCKO signal shift the SDO frame
(status frame) out of the 194-bit shift register with their
rising edges. The LDI high signal latches the SDI frame
(GS or DC frame) from the 194-bit shift register into
corresponding FS, EN, GS or DC registers, and loads the
SDO frame (status frame) from the OT and LED fault flag
registers to the 194-bit shift register at the same time.
The LDO signal is a buffered version of the LDI signal
with certain delay added to match the delay between the
SCKI and SCKO signals. Therefore, a daisy-chain type loop
communication with simultaneous writing and reading
capability is implemented.
Figure 3 illustrates the timing relation among serial
input and serial output signals in more detail. One DC
frame followed by another GS frame is sent through
the LDI, SCKI, and SDI signals. At the same time, two
status frames are received through the LDO, SCKO, and
SDO signals. The rising edges of the SCKI signal shift
a frame of 194-bit data at the SDI pin into the 194-bit
shift register SR[0:193]. After 194 clock cycles, all the
194-bit data sit in the right place waiting for the LDI
signal. An asynchronous LDI high signal latches the
1-bit FS register, 1-bit EN register, and individual 12-bit
GS registers (when FS = 0) or 6-bit DC registers (when
FS = 1) for each channel. At the same time, a frame of
status information, including over temperature flag and
individual open/short LED fault flags, is parallel loaded
into the 194-bit shift register and will be shifted out with
the coming clock cycles.
3745f
14
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