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参数资料
| 型号： | LT3751IFE#TRPBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO20 |
| 封装： | 4.40 MM, LEAD FREE, PLASTIC, TSSOP-20 |
| 文件页数： | 15/34页 |
| 文件大小： | 403K |
| 代理商： | LT3751IFE#TRPBF |
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LT3751
22
3751fb
APPLICATIONS INFORMATION
Large Signal Stability
Large signal stability can be an issue when audible noise
is a concern. Figure 12 shows that the problem originates
from the one-shot clock and the output voltage ripple. The
load must be constrained such that the output voltage
ripple does not exceed the regulation range of the error
amplier within one clock period (approximately 6mV
referred to the FB pin).
The output capacitance should be increased if oscillations
occur or audible noise is present. Use Figure 13 to determine
the maximum load for a given output capacitance to
maintain low audible noise operation. A small capacitor
can also be added from the FB pin to ground to lower the
ripple injected into FB pin.
Small Signal Stability
The LT3751’s error amplier is internally compensated to
increase its operating range but requires the converter’s
output node to be the dominant pole. Small signal stability
constraints become more prevalent during heavy loading
conditions where the dominant output pole moves to
higher frequency and closer to the internal feedback
poles and zeros. The feedback loop requires the output
pole frequency to remain below 200Hz to guarantee small
signal stability. This allows smaller RLOAD values than the
large signal constraint. Thus, small signal issues should
not arise if the large signal constraint is met.
Board Layout
The high voltage operation of the LT3751 demands careful
attention to the board layout, observing the following
points:
1. Minimize the area of the high voltage end of the
secondary winding.
2. Provide sufcient spacing for all high voltage nodes
(NMOS drain, VOUT and secondary winding of the
transformer) in order to meet the breakdown voltage
requirements.
3. Keep the electrical path formed by CVTRANS, the primary
of T1, and the drain of the NMOS as short as possible.
Increasing the length of this path effectively increases
the leakage inductance of T1, potentially resulting in an
overvoltage condition on the drain of the NMOS.
4. Reduce the total node capacitance on the RVOUT and
RDCM pins by removing any ground or power planes
underneath the RDCM and RVOUT pads and traces.
Parasitic capacitance can cause unwanted behavior
on these pins.
5. Thermal vias should be added underneath the
Exposed Pad, Pin 21, to enhance the LT3751’s thermal
performance. These vias should go directly to a large
area of ground plane.
6. Isolated applications require galvanic separation of the
output-side ground and primary-side ground. Adequate
spacing between both ground planes is needed to meet
voltage safety requirements.
Figure 13. COUT(MIN) vs Output Power
OUTPUT POWER (W)
0
C
OUT
,MIN
(μF)
30
25
15
5
20
10
0
150
3751 F14
200
50
100
VOUT = 150V
VOUT = 300V
VOUT = 600V
Figure 12. Voltage Ripple Stability Constraint
VOUT
3751 F13
26kHz
ONE-SHOT
CLK
IPRI
LOAD
DROOP
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LT3751IUFD | 制造商:LINER 制造商全称:Linear Technology 功能描述:Capacitor Charger Controller with Regulation |
| LT3751IUFD#PBF | 功能描述:IC CTRLR CAP CHRGR 4.75V 20-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 电源管理 - 专用 系列:- 标准包装:1 系列:- 应用:手持/移动设备 电流 - 电源:- 电源电压:3 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:14-WFDFN 裸露焊盘 供应商设备封装:14-LLP-EP（4x4） 包装:Digi-Reel® 配用:LP3905SD-30EV-ND - BOARD EVALUATION LP3905SD-30 其它名称:LP3905SD-30DKR |
| LT3751IUFD#TRPBF | 功能描述:IC CTRLR CAP CHRGR 4.75V 20-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 电源管理 - 专用 系列:- 标准包装:1 系列:- 应用:手持/移动设备 电流 - 电源:- 电源电压:3 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:14-WFDFN 裸露焊盘 供应商设备封装:14-LLP-EP（4x4） 包装:Digi-Reel® 配用:LP3905SD-30EV-ND - BOARD EVALUATION LP3905SD-30 其它名称:LP3905SD-30DKR |
| LT3751IUFD-PBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:Capacitor Charger Controller with Regulation |
| LT3751IUFD-TR | 制造商:LINER 制造商全称:Linear Technology 功能描述:Capacitor Charger Controller with Regulation |
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