参数资料
型号: LT3751IFE#TRPBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 电源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO20
封装: 4.40 MM, LEAD FREE, PLASTIC, TSSOP-20
文件页数: 8/34页
文件大小: 403K
代理商: LT3751IFE#TRPBF
LT3751
16
3751fb
APPLICATIONS INFORMATION
The total propagation delay, td,isthesecondmostdominant
factor that affects efciency and is the summation of gate
driver on-off propagation delays and the discharge time
associated with the secondary winding capacitance. There
are two effective methods to reduce the total propagation
delay. First, reduce the total capacitance on the secondary
winding, most notably the diode capacitance. Second,
reduce the total required NMOS gate charge. Figure 8
shows the effect of large secondary capacitance.
The energy stored in the secondary winding capacitance
is CSEC VOUT2. This energy is reected to the
primary when the diode stops forward conduction. If the
reected capacitance is greater than the total NMOS drain
capacitance, the drain of the NMOS power switch goes
negative and its intrinsic body diode conducts. It takes
some time for this energy to be dissipated and thus adds
to the total propagation delay.
Choosing Regulator Maximum IPK
The IPK parameter in regulation mode is calculated based
on the desired maximum output power instead of charge
time like that in a capacitor charger application.
I
PK = 2
P
OUT(AVG)
Efficiency
1
V
TRANS
+
N
V
OUT
Note that the LT3751 regulation scheme varies the peak
current based on the output load current. The maximum
IPK is only reached during charge mode or during heavy
load conditions where output power is maximized.
Figure 8. Effect of Secondary Winding Capacitance
VDRAIN
3751 F08
ISEC
IPRI
NO SEC.
CAPACITANCE
SEC. DISCHARGE
t
Transformer Design
The transformer’s primary inductance, LPRI, is determined
by the desired VOUT and previously calculated N and IPK
parameters. Use the following equation to select LPRI:
L
PRI =
3
μs V
OUT
I
PK N
The previous equation guarantees that the VOUTcomparator
has enough time to sense the yback waveform and trip
the DONE pin latch. Operating VOUT signicantly higher
than that used to calculate LPRI could result in a runaway
condition and overcharge the output capacitor.
The LPRI equation is adequate for most regulator
applications. Note that if both IPK and N are increased
signicantly for a given VTRANS and VOUT, the maximum
IPK will not be reached within the refresh clock period. This
will result in a lower than expected maximum output power.
To prevent this from occurring, maintain the condition in
the following equation.
L
PRI <
38
μs
I
PK
1
V
TRANS
+
N
V
OUT
The upper constraint on LPRI can be reduced by increasing
VTRANS and starting the design process over. The best
regulation occurs when operating the boundary-mode
frequency above 100kHz (refer to Operation section for
boundary-mode denition).
Figure 9 denes the maximum boundary-mode switching
frequency when operating at a desired output power level
and is normalized to LPRI/POUT (μH/Watt). The relationship
of output power, boundary-mode frequency, IPK, and
primary inductance can be used as a guide throughout
the design process.
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