参数资料
型号: LT3781IG#TRPBF
厂商: Linear Technology
文件页数: 14/20页
文件大小: 0K
描述: IC REG CTRLR ISO PWM CM 20-SSOP
标准包装: 1,800
PWM 型: 电流模式
输出数: 2
频率 - 最大: 700kHz
占空比: 100%
电源电压: 8 V ~ 72 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 20-SSOP(0.209",5.30mm 宽)
包装: 带卷 (TR)
LT3781
APPLICATIO S I FOR ATIO
Shutdown
The LT3781 SHDN pin will support TTL and CMOS logic
signals and also analog inputs. The SHDN pin turn-on
(rising) threshold is 1.25V with 150mV of hysteresis. A
common use of the SHDN pin is for under voltage detec-
tion on the input supply. Driving the SHDN pin with a
resistor-divider connected from the input supply to ground
will prevent switching until the desired input supply volt-
age is achieved.
An 18V clamp on the V CC pin is enabled during shutdown
mode, preventing a trickle start circuit from pulling that pin
above maximum operational levels.
The LT3781 enters an ultralow current shutdown mode
when the SHDN pin is below 350mV. During this mode,
total supply current drops to a typical value of 16 μ A. When
SHDN rises above 350mV, the IC will draw increasing
amounts of supply current until just before the 1.25V
turn-on threshold is achieved, when the supply current
reaches 75 μ A.
The shutdown function can be disabled by connecting the
SHDN pin to V CC . This pin is internally clamped to 2.5V
through a 20k series input resistance and can therefore
draw almost 1mA when tied directly to the V CC supply. This
additional current can be minimized by making the con-
nection through an external series resistor (100k is typi-
cally used).
Soft-Start
The LT3781 current control pin (V C ) limits sensed current
to zero at voltage less than 1.4V through full current limit
at V C = 3.2V, yielding 1.8V over the full regulation range.
The voltage on the V C pin is internally forced to be less than
or equal to SS + 0.7V. As such, the SS pin has a “dead
zone” between 0V and 0.7V, where a zero sensed current
condition is maintained. At SS voltages above 0.7V, the
sensed current limit threshold on the V C pin may rise as
needed up to the SS maintained current limit value. Once
the SS pin rises to the V C pin maximum value less 0.7V, or
2.5V, the SS circuit has no effect.
The SS pin sources a typical current of 10 μ A. Placing a
capacitor (C SS ) from the SS pin to ground will cause the
voltage on the SS pin to ramp up at a controlled rate,
allowing a graceful increase of maximum converter output
current during a start-up condition. The start-up delay
time to full available current limit is:
t SS = 2.5 ? 10 5 ? C SS (sec)
The LT3781 internally pulls the SS pin below the zero
current threshold during any fault condition to assure
graceful recovery. The SS circuit also acts as a fault control
latch to assure a full-range recovery from a short duration
fault. Once a fault condition is detected, the LT3781 will
suspend switching until the SS pin has discharged to
approximately 225mV.
Layout Considerations-Grounding
The LT3781 is typically used in high current converter
designs that involve substantial switching transients. The
switch drivers on the IC are designed to drive large
capacitances and, as such, generate significant transient
currents. Careful consideration must be made regarding
input and local power supply bypassing to avoid corrupt-
ing the ground references used by the error amplifier and
current sense circuitry.
Effective grounding of the two-transistor synchronous
forward topology where the LT3781 is used is inherently
difficult. The situation is complicated further by the num-
ber of bypass elements that must be considered.
Typically, high current paths and transients from the input
supply and any local drive supplies must be kept isolated
from SGND, to which sensitive circuits such as the error
amp reference and the current sense circuits, as well as the
local 5V REF supply, are referred. By virtue of the topologies
used in LT3781 applications, the large currents from the
primary switches, as well as the switch drive transients,
pass through the sense resistor to ground. This defines
the ground connection of the sense resistor as the refer-
ence point for both SGND and PGND. In nonisolated
applications where SGND is the output reference, we now
have a condition where every bypass capacitor in the
converter is referenced to the same point.
3781f
14
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