参数资料
型号: LT3844IFE#TRPBF
厂商: Linear Technology
文件页数: 9/24页
文件大小: 0K
描述: IC REG CTRLR BST INV PWM 16TSSOP
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 330kHz
占空比: 95%
电源电压: 4 V ~ 60 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 带卷 (TR)
LT3844
OPERATION
(Refer to Functional Diagram)
To eliminate the possibility of shoot through between the
MOSFET and the internal SW pull-down switch, an adap-
tive nonoverlap circuit ensures that the internal pull-down
switch does not turn on until the gate of the MOSFET is
below its turn on threshold.
Low Current Operation (Burst Mode Operation)
To increase low current load ef?ciency, the LT3844 is
capable of operating in Linear Technology’s proprietary
Burst Mode operation where the external MOSFET operates
intermittently based on load current demand. The Burst
Mode function is disabled by connecting the BURST_EN
pin to V CC or V FB and enabled by connecting the pin to
SGND.
When the required switch current, sensed via the V C pin
voltage, is below 15% of maximum, Burst Mode operation
is employed and that level of sense current is latched onto
the IC control path. If the output load requires less than
this latched current level, the converter will overdrive the
output slightly during each switch cycle. This overdrive
condition is sensed internally and forces the voltage on the
V C pin to continue to drop. When the voltage on V C drops
150mV below the 15% load level, switching is disabled,
and the LT3844 shuts down most of its internal circuitry,
reducing total quiescent current to 120μA. When the
converter output begins to fall, the V C pin voltage begins
to climb. When the voltage on the V C pin climbs back to
the 15% load level, the IC returns to normal operation and
switching resumes. An internal clamp on the V C pin is set
at 100mV below the output disable threshold, which limits
the negative excursion of the pin voltage, minimizing the
converter output ripple during Burst Mode operation.
During Burst Mode operation, the V IN pin current is 20μA
and the V CC current is reduced to 100μA. If no external
drive is provided for V CC , all V CC bias currents originate
from the V IN pin, giving a total V IN current of 120μA. Burst
current can be reduced further when V CC is driven using an
output derived source, as the V CC component of V IN current
is then reduced by the converter duty cycle ratio.
Start-Up
The following section describes the start-up of the supply
and operation down to 4V once the step-down supply is
up and running. For the protection of the LT3844 and the
switching supply, there are internal undervoltage lockout
(UVLO) circuits with hysteresis on V IN , V CC and V BOOST ,
as shown in the Electrical Characteristics table. Start-up
and continuous operation require that all three of these
undervoltage lockout conditions be satis?ed because the
TG MOSFET driver is disabled during any UVLO fault con-
dition. In start-up, for most applications, V CC is powered
from V IN through the high voltage linear regulator of the
LT3844. This requires V IN to be high enough to drive the
V CC voltage above its undervoltage lockout threshold.
V CC , in turn, has to be high enough to charge the BOOST
capacitor through an external diode so that the BOOST
voltage is above its undervoltage lockout threshold. There
is an NPN switch that pulls the SW node to ground each
cycle during the TG power MOSFET off-time, ensuring the
BOOST capacitor is kept fully charged. Once the supply
is up and running, the output voltage of the supply can
backdrive V CC through an external diode. Internal circuitry
disables the high voltage regulator to conserve V IN supply
current. Output voltages that are too low or too high to
backdrive V CC require additional circuitry such as a voltage
doubler or linear regulator. Once V CC is backdriven from
a supply other than V IN , V IN can be reduced to 4V with
normal operation maintained.
Soft-Start
The soft-start function controls the slew rate of the power
supply output voltage during start-up. A controlled output
voltage ramp minimizes output voltage overshoot, reduces
inrush current from the V IN supply, and facilitates supply
sequencing. A capacitor, C SS , connected from the C SS pin
to SGND, programs the slew rate. The capacitor is charged
from an internal 2μA current source producing a ramped
voltage. The capacitor voltage overrides the internal refer-
ence to the error ampli?er. If the V FB pin voltage exceeds
3844fb
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