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参数资料
| 型号： | LT4220CGN#TR |
| 厂商： | Linear Technology |
| 文件页数： | 8/16页 |
| 文件大小： | 259K |
| 描述： | IC CTLR HOTSWAP DUAL 16-SSOP |
| 标准包装： | 2,500 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | 2.7 V ~ 16.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SSOP |
| 包装： | 带卷 (TR) |
8
LT4220
4220f
U
U
PI FU CTIO S
FAULT pin to the ON
+
pin, otherwise the part remains
latched off.
To disable the timeout circuit breaker, connect the TIMER
pin to GND.
GND (Pin 9): Supply Ground Pin.
PWRGD (Pin 10): Open-Collector Output to GND. PWRGD
goes to high impedance after the initial GATE
and final
GATE
+
pins
have reached their maximum voltage and after
the FB
+
pin goes above 1.24V low-to-high threshold and
after the FB
pin falls below 1.24V high-to-low threshold.
An external pull-up resistor can pull the pin to a voltage
higher or lower than V
CC
. If not used, PWRGD can be left
floating or tied to GND.
FAULT (Pin 11): Open-Collector Output to GND. The
FAULT pin is pulled low whenever the TIMER pin rises
above V
TIMERH
(1.24V) threshold, thereby setting the
internal fault latch. It goes to high impedance whenever the
internal fault latch is reset. The fault latch is reset with
either internal undervoltage lockout conditions, or by the
ON comparators if the TIMER pin is also below 0.5V. If not
used, the FAULT pin can be left floating or tied to GND.
ON
+
(Pin 12): Positive Supply Good Comparator Input. It
monitors the positive input voltage (V
CC
) with an external
resistive divider for undervoltage lockout. When the volt-
age on ON
+
is above the V
ON
+
H
high-to-low threshold
(1.24V) the positive supply is considered good. If ON
+
drops below 1.185V, both GATE
and GATE
+
are pulled
low.
If ON
+
is pulled low after a current limit fault and when the
TIMER pin is below 0.5V, the fault latch is reset allowing
the part to turn back on. Typically the FAULT pin is tied
back to the ON
+
pin for autorestart. If not used, the ON
+
pin
should be set to a voltage in the range of 1.3V < ON
+
< V
CC
+ 0.3V. The ON
+
pin requires a bypass capacitor connected
to ground.
FB
+
(Pin 13): Positive Power Good Comparator Input. This
pin monitors the positive output voltage (V
OUT
+) with an
external resistor divider. When the voltage on FB
+
is above
the V
FB
+
H
low-to-high threshold (1.24V) and the GATE
+
drive voltage has reached a maximum, the PWRGD is
released. PWRGD is pulled low when the FB
+
pin is below
1.185V. The PWRGD pin is wire-ORed with the FB
pin
conditions.
FB
+
also controls the positive current limit sense amplifier
input offset to provide foldback current limit. The FB
+
pin
linearly reduces the positive sense amplifier offset from
48mV to 15mV for FB
+
in the range 0.85V > FB
+
> 0V. If
PWRGD and foldback current limit are not used, the FB
+
pin should be set to a voltage in the range of 1.3V < FB
+
<
V
CC
+ 0.3V.
GATE
+
(Pin 14): High Side Gate Drive for the External
Positive Supply N-Channel FET. An internal charge pump
guarantees at least 3.5V above V
CC
, for supply voltages at
?.7V increasing to a minimum of 5V above V
CC
for supply
voltages greater than ?V. A 10礎 pull-up current source
drives the pin. An external capacitor connected from the
GATE
+
pin to GND will control the rising slope of the GATE
+
signal. The voltage is clamped to 7V above V
CC
.
When the current limit is reached, the GATE
+
pin voltage
will be adjusted to maintain a constant voltage across the
R
S
+
resistor while the timer capacitor starts to charge. If
the TIMER pin voltage exceeds 1.24V, the GATE
+
pin will
be pulled low.
The GATE
+
pin is pulled to GND whenever the ON
+
pin is
below 1.24V, the ON
pin is above 1.24V, either supply is
in the undervoltage lockout voltage range, or the TIMER
pin rises above 1.24V.
SENSE
+
(Pin 15): Positive Supply Current Limit Sense Pin.
A sense resistor must be placed in the supply path be-
tween V
CC
and SENSE
+
. The current limit circuit will
regulate the voltage across the sense resistor to 50mV
(V
CC
SENSE
+
) when the FB
+
voltage is greater than
0.85V. If V
FB
+
goes below 0.85V, the voltage across the
sense resistor decreases linearly and stops at 15mV when
V
FB
+
is 0V.
V
CC
(Pin 16): Positive Supply. The positive supply input
ranges from 2.7V to 16.5V for normal operation. I
CC
is
typically 2.7mA. An internal undervoltage lockout circuit
disables the chip for inputs less than 2.45V. Place a 0.1礔
bypass capacitor next to the V
CC
pin.
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相关代理商/技术参数 |
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| LT4220IGN | 功能描述:IC CTLR HOTSWAP DUAL 16-SSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:100 系列:- 类型:热插拔开关 应用:通用 内部开关:是 电流限制:可调 电源电压:9 V ~ 13.2 V 工作温度:-40°C ~ 150°C 安装类型:表面贴装 封装/外壳:10-WFDFN 裸露焊盘 供应商设备封装:10-TDFN-EP（3x3） 包装:管件 |
| LT4220IGN#PBF | 功能描述:IC CTLR HOTSWAP DUAL 16-SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:100 系列:- 类型:热插拔开关 应用:通用 内部开关:是 电流限制:可调 电源电压:9 V ~ 13.2 V 工作温度:-40°C ~ 150°C 安装类型:表面贴装 封装/外壳:10-WFDFN 裸露焊盘 供应商设备封装:10-TDFN-EP（3x3） 包装:管件 |
| LT4220IGN#TR | 功能描述:IC CTLR HOTSWAP DUAL 16-SSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:100 系列:- 类型:热插拔开关 应用:通用 内部开关:是 电流限制:可调 电源电压:9 V ~ 13.2 V 工作温度:-40°C ~ 150°C 安装类型:表面贴装 封装/外壳:10-WFDFN 裸露焊盘 供应商设备封装:10-TDFN-EP（3x3） 包装:管件 |
| LT4220IGN#TRPBF | 功能描述:IC CTLR HOTSWAP DUAL 16-SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:119 系列:- 类型:热交换控制器 应用:通用型，PCI Express? 内部开关:无 电流限制:- 电源电压:3.3V，12V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:80-TQFP 供应商设备封装:80-TQFP（12x12） 包装:托盘 产品目录页面:1423 (CN2011-ZH PDF) |
| LT4239 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:TRANSISTOR | BJT | NPN | TO-129 |
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