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| 型号： | LT4250LIS8#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 8/14页 |
| 文件大小： | 236K |
| 描述： | IC CONTRLR HOTSWAP NEG 48V 8SOIC |
| 标准包装： | 2,500 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | -20 V ~ -80 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 带卷 (TR) |
LT4250L/LT4250H
8
4250lhfa
APPLICATIONS INFORMATION
Figure 6a. Inrush Control Circuitry
Figure 6b. Inrush Control Waveforms
Hot Circuit Insertion
When circuit boards are inserted into a live 48V back-
plane, the bypass capacitors at the input of the boards
power module or switching power supply can draw huge
transient currents as they charge up. The transient currents
can cause permanent damage to the boards components
and cause glitches on the system power supply.
The LT4250 is designed to turn on a boards supply volt-
age in a controlled manner, allowing the board to be safely
inserted or removed from a live backplane. The chip also
provides undervoltage, overvoltage and overcurrent pro-
tection while keeping the power module off until its input
voltage is stable and within tolerance.
Power Supply Ramping
The input to the power module on a board is controlled by
placing an external N-channel pass transistor (Q1) in the
power path (Figure 6a). R1 provides current fault detection
and R2 prevents high frequency oscillations. Resistors R4,
R5 and R6 provide undervoltage and over-voltage sensing.
By ramping the gate of Q1 up at a slow rate, the inrush
current charging load capacitors C3 and C4 can be limited
to a safe value when the board makes connection.
Resistor R3 and capacitor C2 act as a feedback network
to accurately control the inrush current. The C2 capacitor
can be calculated with the following equation:
C2 = (45糀 " C
L
)/I
INRUSH
where C
L
is the total load capacitance = C3 + C4 + module
input capacitance.
Capacitor C1 and resistor R3 prevent Q1 from momentarily
turning on when the power pins first make contact. Without
C1 and R3, capacitor C2 would pull the gate of Q1 up to
a voltage roughly equal to V
EE
" C2/CGS(Q1) before the
LT4250 could power up and actively pull the gate low. By
placing capacitor C1 in parallel with the gate capacitance
of Q1 and isolating them from C2 using resistor R3 the
problem is solved. The value of C1 is given by:
C1=
V
INMAX
V
TH
V
T
H
" C2+C
GD
(
)
C1 E 35 " C2 for V
INMAX
= 72V
where V
TH
is the MOSFETs minimum gate threshold and
V
INMAX
is the maximum operating input voltage.
R3 should not exceed a value that produces an R3 " C2
time-constant of 150約. A 1k value for R3 will ensure this
for C2 values up to 150nF .
The waveforms are shown in Figure 6b. When the power
pins make contact, they bounce several times. While the
contacts are bouncing, the LT4250 senses an undervoltage
condition and the GATE is immediately pulled low when
the power pins are disconnected.
Once the power pins stop bouncing, the GATE pin starts
to ramp up. When Q1 turns on, the GATE voltage is held
constant by the feedback network of R3 and C2. When the
+
V
EE
V
DD
LT4250H
PWRGD
UV = 38.5V
OV = 71V
SENSE
C1
470nF
25V
C3
0.1糉
100V
C4
100糉
100V
C5
100糉
16V
Q1
IRF530
R2
10?/DIV>
5%
R3
1k, 5%
C2
15nF
100V
R4
549k
1%
R5
6.49k
1%
R6
10k
1%
R1
0.02?/DIV>
5%
4
3
2
OV
48V RTN
48V RTN
(SHORT PIN)
48V
UV
5
6
8
7
1
GATE
DRAIN
VICOR
VI-J30-CY
V
OUT
+
V
OUT
V
IN
+
5V
4250 F06a
GATE IN
V
IN
+
*
* DIODES INC. SMAT70A
4
3
2
1
INRUSH
CURRENT
500mA/DIV
GATE V
EE
10V/DIV
DRAIN
50V/DIV
V
EE
50V/DIV
25ms/DIV
4250 F06b
CONTACT
BOUNCE
MODULE
TURN-ON
MODULE
TURN-ON
CONTACT
BOUNCE
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