参数资料
型号: LT4256-1CS8#TRPBF
厂商: Linear Technology
文件页数: 10/16页
文件大小: 213K
描述: IC CTRLR HOTSWAP HV LATCH 8SOIC
标准包装: 2,500
类型: 热交换控制器
应用: 通用
内部开关:
电源电压: 10.8 V ~ 80 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
LT4256-1/LT4256-2
10
425612fa
APPLICATIO  S I FOR  ATIO
U
U
U
Figure 7. Current Limit Sense Voltage vs Feedback Pin Voltage
Figure 8. Response Time to Overcurrent
Figure 11 shows how the LT4256-1/LT4256-2 are com-
manded to shut off with a logic signal. This is accom-
plished by pulling the gate of the open-drain MOSFET, Q2,
(tied to the UV pin) high.
Short-Circuit Protection
The LT4256-1/LT4256-2 features a programmable foldback
current limit with an electronic circuit breaker that protects
against short circuits or excessive load currents. The
current limit is set by placing a sense resistor (R5)
between V
CC
 and SENSE. The current limit threshold is
calculated as:
I
LIMIT
 = 55mV/R5
(5)
where R5 is the sense resistor.
To limit excessive power dissipation in the pass transistor
and to reduce voltage spikes on the input supply during
short-circuit conditions at the output, the current folds
back as a function of the output voltage, which is sensed
internally on FB.
If the LT4256-1/LT4256-2 go into current limit when the
voltage on FB is 0V, the current limit circuit drives the
GATE pin to force a constant 14mV drop across the sense
resistor. As the output at FB increases, the voltage across
the sense resistor increases until the FB pin reaches 2V, at
which point the voltage across the sense resistor is held
constant at 55mV (see Figure 7).
For a 0.025& sense resistor, the current limit is set at
2200mA and folds back to 560mA when the output is
shorted to ground. Thus, MOSFET peak power dissipation
under short-circuit conditions is reduced from 105.6W to
26.5W. See the Layout Considerations section for impor-
tant information about board layout to minimize current
limit threshold error.
The LT4256-1/LT4256-2 also features a variable
overcurrent response time. The time required for the part
to regulate the GATE voltage is a function of the voltage
across the sense resistor connected between V
CC
 and
SENSE. This helps to eliminate sensitivity to current
spikes and transients that might otherwise unnecessarily
trigger a current limit response and increase MOSFET
dissipation. Figure 8 shows the response time as a func-
tion of the overdrive at SENSE.
TIMER
TIMER provides a method for programming the maximum
time the part is allowed to operate in current limit. When
the current limit circuitry is not active, the TIMER pin is
pulled to GND by a 3礎 current source. When the current
limit circuitry becomes active, a 108礎 pull-up current
source is connected to TIMER and the voltage will rise with
a slope equal to 105礎/C
TIMER
 as long as the circuitry
stays active. Once the desired maximum current limit time
is known, the capacitor value is:
nF
t ms  C
A
V
t
[   ]
" [   ];
.
"
=
=
?/DIV>
25
105
4
(6)
14mV
0V
2V
FB
4256 F07
55mV
V
CC
  V
SENSE
50
100
150
200
4256 F08
12
10
8
6
4
2
V
CC
  V
SENSE
(mV)
0
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