参数资料
型号: LT5554IUH#PBF
厂商: Linear Technology
文件页数: 19/32页
文件大小: 0K
描述: IC VGA DIG CONTROL 32-QFN
标准包装: 73
应用: 可变增益(VGA)
电路数: 1
-3db带宽: 1GHz
电流 - 电源: 200mA
电压 - 电源,单路/双路(±): 4.75 V ~ 5.25 V
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-QFN 裸露焊盘(5x5)
包装: 管件
产品目录页面: 1322 (CN2011-ZH PDF)
LT5554
26
5554f
Figure 20. Timing Test for PG6 and STROBE (Simplied Schematic)
J6
J7
VDEC
32
PG1
31
GND
30
PG2
29
PG3
PG1
PG2
PG3
28
GND
27
PG4
26
GND
25
GND
9
PG5
10
GND
11
PG6
12
PG0
PG6
PG0
13
GND
14
STROBE
15
GND
16
GND
1
GND
2
GND
3
DEC
4
IN+
5
IN
6
DEC
7
GND
8
GND
24
VCC
23
ENB
ENABLE
22
GND
21
OUT
20
OUT+
19
GND
18
MODE
17
VCC
LT5554
C6
47nF
C8
0.1μF
C5
1μF
C17
47nF
C28
47nF
R17
100Ω
R33
100Ω
R34
100Ω
R27
R22
10k
R23
10k
R29
R30
R32
R26
10k
R20
10k
R25
10k
C16
47nF
R16
100Ω
R21
10k
R24
10k
R28
R31
R8
5554 F20
C4
0.1μF
C27
47nF
C88
47nF
VPG
APPLICATIONS INFORMATION
Evaluation Board
Figure 21 shows the schematic of the LT5554 evaluation
board. Transformer T2 is TC2-1T and resistor R5 + R6 =
134Ω (ROUT = 50Ω GP(J3) = 13.2dB). The silkscreen and
layout are shown in Figures 22 through Figure 27. The
board control J5 edge connector (40PINS SMT-TB) allows
easy access to LT5554 component pins. Alternatively or
combined with J5, 14 test points (turrets) for signals and
two for GND are also available. The board is powered with
a single supply in 4.75V to 5.25V at VCC and VCCO (either
J5 connector or turrets). Connecting the ENABLE pin to
VCC supply enables the LT5554 part. PGx gain control
and STROBE inputs will have TTL levels (DC-coupled)
when MODE = 5V (same power supply). To set LT5554 for
maximum gain (GMAX) in transparent-mode, all seven PGx
and STROBE can be connected to 5V supply. Alternatively,
a 2.2V power supply at VPG pin and STROBE turret will
set same GMAX state.
J1 (input) and J3 (output) are the default board signal
ports for evaluation with 50Ω single ended test system. For
differential evaluation, the board J11 and J33 connectors
must be recongured.
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