参数资料
型号: LTC1043CN#PBF
厂商: Linear Technology
文件页数: 5/16页
文件大小: 0K
描述: IC BUILDNG BLK SW-CAP DUAL 18DIP
标准包装: 20
应用: 仪表
输入电压: 3 V ~ 18 V
输出数: 2
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 18-DIP(0.300",7.62mm)
供应商设备封装: 18-DIP
包装: 管件
产品目录页面: 1356 (CN2011-ZH PDF)
LTC1043
TEST CIRCUITS
Test Circuit 1. Leakage Current Test
Test Circuit 2. R ON Test
(7, 13, 6, 18)
(8, 14, 5, 15)
(7, 13, 6, 18)
(8, 14, 5, 15)
NOTE: TO OPEN SWITCHES,
0V TO 10V
A
+
(11, 12, 2, 3)
S1 AND S3
SHOULD BE CONNECTED
TO V –. TO OPEN S2, S4,
C OSC PIN SHOULD BE
TO V+ C OSC
+
VIN
100 μ A to 1mA
A
(11, 12, 2, 3)
LTC1043 ? TC01
CURRENT SOURCE
LTC1043 ? TC02
Test Circuit 3. Oscillator Frequency, f OSC
Test Circuit 4. CMRR Test
7
8
V OUT
(TEST PIN) 2
V+
4
+
LTC1043
V–
17
16
C OSC
10
11
1 μ F
+
1 μ F
CAPACITORS ARE
NOT ELECTROLYTIC
5
12
+
IV
6
13
14
LTC1043 ? TC03
+
V – ≤ V CM ≤ V +
( )
CMRR = 20 LOG
V CM
V OUT
NOTE: FOR OPTIMUM CMRR, THE C OSC SHOULD
BE LARGER THAN 0.0047 μ F, AND
THE SAMPLING CAPACITOR ACROSS
PINS 11 AND 12 SHOULD BE PLACED
APPLICATIO S I FOR ATIO
OVER A SHIELD TIED TO PIN 10
LTC1043 ? TC04
Common Mode Rejection Ratio (CMRR)
1/2 LTC1043
The LTC1043, when used as a differential to single-ended
converter rejects common mode signals and preserves
differential voltages (Figure 1). Unlike other techniques,
7
C + 11
8
the LTC1043’s CMRR does not degrade with increasing
common mode voltage frequency. During the sampling
V D
+
C S
V D
+
C H
mode, the impedance of Pins 2, 3 (and 11, 12) should be
reasonably balanced, otherwise, common mode signals
C – 12
will appear differentially. The value of the CMRR depends
on the value of the sampling and holding capacitors
(C S , C H ) and on the sampling frequency. Since the
V CM
+
13
14
common mode voltages are not sampled, the
common mode signal frequency can well exceed the
sampling frequency without experiencing aliasing
phenomena. The CMRR of Figure 1 is measured by
C S , C H ARE MYLAR OR POLYSTRENE
LTC1043 ? AI01
Figure 1. Differential to Single-Ended Converter
1043fa
5
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