参数资料
型号: LTC1098CN8#PBF
厂商: Linear Technology
文件页数: 20/32页
文件大小: 0K
描述: IC A/D CONV 8BIT SRL IN/OUT 8DIP
标准包装: 50
位数: 8
采样率(每秒): 33k
数据接口: 串行
转换器数目: 1
功率耗散(最大): 780µW
电压电源: 单电源
工作温度: 0°C ~ 70°C
安装类型: 通孔
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-PDIP
包装: 管件
输入数目和类型: 1 个差分,单极
产品目录页面: 1345 (CN2011-ZH PDF)
LTC1096/LTC1096L
LTC1098/LTC1098L
27
10968fc
TYPICAL APPLICATIONS
Interfacing to the Parallel Port of the
Intel 8051 Family
The Intel 8051 has been chosen to demonstrate the
interface between the LTC1098(L) and parallel port mi-
croprocessors. Normally the CS, CLK and DIN signals
would be generated on three port lines and the DOUT signal
read on a fourth port line. This works very well. However,
we will demonstrate here an interface with the DIN and
DOUT of the LTC1098(L) tied together as described in the
SERIAL INTERFACE section. This saves one wire.
The 8051 rst sends the start bit and MUX address to the
LTC1098(L) over the data line connected to P1.2. Then
P1.2 is recongured as an input (by writing to it a one) and
the 8051 reads back the 8-bit A/D result over the same
data line.
DOUT from LTC1098(L) Stored in 8051 RAM
CS
CLK
DOUT
DIN
LTC1098(L)
ANALOG
INPUTS
P1.4
P1.3
P1.2
8051
MUX ADDRESS
A/D RESULT
10968 TA06
R2
10968 TA07
MSB
LSB
B7
B6
B5
B4
B3
B2
B1
B0
1
CS
CLK
DATA (DIN/DOUT)
START
ODD/
SIGN
MSBF
B7
MSBF BIT LATCHED
BY LTC1098(L)
LTC1098(L) SENDS A/D RESULT
BACK TO 8051 P1.2
8051 P1.2 OUTPUTS DATA
TO LTC1098(L)
8051 P1.2 RECONFIGURED
AS AN INPUT AFTER THE 4TH RISING
CLK AND BEFORE THE 4TH FALLING CLK
LTC1098(L) TAKES CONTROL OF DATA LINE
ON 4TH FALLING CLK
23
4
SGL/
DIFF
B6
B5
B4
B3
B2
B1
B0
10968 TA08
LABEL
MNEMONIC
OPERAND
COMMENTS
LOOP 1
LOOP
MOV
SETB
CLR
MOV
RLC
CLR
MOV
SETB
DJNZ
MOV
CLR
MOV
RLC
SETB
CLR
DJNZ
MOV
SETB
A, #FFH
P1.4
R4, #04
A
P1.3
P1.2, C
P1.3
R4, LOOP 1
P1, #04
P1.3
R4, #09
C, P1.2
A
P1.3
R4, LOOP
R2, A
P1.4
DIN word for LTC1098(L)
Make sure CS is high
CS goes low
Load counter
Rotate DIN bit into Carry
CLK goes low
Output DIN bit to LTC1098(L)
CLK goes high
Next bit
Bit 2 becomes an input
CLK goes low
Load counter
Read data bit into Carry
Rotate data bit into Acc.
CLK goes high
CLK goes low
Next bit
Store MSBs in R2
CS goes high
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